top.fit.qmsg

基于FPGA的多波形发生器（编程环境QuartusII6.0）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 19 17:25:29 2007 " "Info: Processing started: Tue Jun 19 17:25:29 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off top -c top " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off top -c top" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "top EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design top" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "12 30 " "Info: No exact pin location assignment(s) for 12 pins of 30 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[7\] " "Info: Pin out\[7\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[7\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[7] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[6\] " "Info: Pin out\[6\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[6\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[6] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[5\] " "Info: Pin out\[5\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[5\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[5] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[4\] " "Info: Pin out\[4\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[4\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[4] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[3\] " "Info: Pin out\[3\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[3\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[3] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[2\] " "Info: Pin out\[2\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[2\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[2] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[1\] " "Info: Pin out\[1\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[1\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[1] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "out\[0\] " "Info: Pin out\[0\] not assigned to an exact location on the device" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 112 1008 1184 128 "out\[7..0\]" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "out\[0\]" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { out[0] } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { out[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { altera_reserved_tdo } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { altera_reserved_tms } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { altera_reserved_tck } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { altera_reserved_tdi } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal altera_internal_jtag~TCKUTAP to use Global clock" {  } { { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock " "Info: Automatically promoted some destinations of signal clk to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tf_top:inst4\|conter8:inst\|inst2 " "Info: Destination tf_top:inst4\|conter8:inst\|inst2 may be non-global or may not use global clock" {  } { { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 56 152 216 104 "inst2" "" } } } }  } 0}  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 264 -120 48 280 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clk " "Info: Pin clk drives global clock, but is not placed in a dedicated clock pin position" {  } { { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 264 -120 48 280 "clk" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { clk } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "tf_top:inst4\|tf_ctro:inst1\|inst8~0 Global clock " "Info: Automatically promoted some destinations of signal tf_top:inst4\|tf_ctro:inst1\|inst8~0 to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tf_top:inst4\|tf_ctro:inst1\|inst8~99 " "Info: Destination tf_top:inst4\|tf_ctro:inst1\|inst8~99 may be non-global or may not use global clock" {  } { { "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" { { 24 592 656 72 "inst8" "" } } } }  } 0}  } { { "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" { { 24 592 656 72 "inst8" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 Global clock " "Info: Automatically promoted some destinations of signal tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 " "Info: Destination tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 may be non-global or may not use global clock" {  } { { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tf_top:inst4\|tf_ctro:inst1\|74154:inst\|23~14 " "Info: Destination tf_top:inst4\|tf_ctro:inst1\|74154:inst\|23~14 may be non-global or may not use global clock" {  } { { "c:/altera/quartus41/libraries/others/maxplus2/74154.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74154.bdf" { { 1048 720 784 1152 "23" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tf_top:inst4\|tf_ctro:inst1\|inst8~98 " "Info: Destination tf_top:inst4\|tf_ctro:inst1\|inst8~98 may be non-global or may not use global clock" {  } { { "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" { { 24 592 656 72 "inst8" "" } } } }  } 0}  } { { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 Global clock " "Info: Automatically promoted signal sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 to use Global clock" {  } { { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0}