top.tan.summary

基于FPGA的多波形发生器（编程环境QuartusII6.0）

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.912 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.597 ns
From           : tf_top:inst4|74374:inst4|15
To             : L[3]
From Clock     : clk2
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 14.142 ns
From           : n1
To             : out[2]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.847 ns
From           : altera_internal_jtag
To             : SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.340 ns
From           : tf_top:inst4|74374:inst4|16
To             : L[6]
From Clock     : clk2
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk2'
Slack          : N/A
Required Time  : None
Actual Time    : 27.39 MHz ( period = 36.506 ns )
From           : tf_top:inst4|conter8:inst|74390:inst|32
To             : tf_top:inst4|74374:inst4|19
From Clock     : clk2
To Clock       : clk2
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 56.92 MHz ( period = 17.570 ns )
From           : tf_top:inst4|conter8:inst|74390:inst|33
To             : tf_top:inst4|conter8:inst|74390:inst|31
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 91.74 MHz ( period = 10.900 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2]
To             : sld_hub:sld_hub_inst|HUB_TDO~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'clk2'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : tf_top:inst4|conter8:inst|74390:inst|33
To             : tf_top:inst4|conter8:inst|74390:inst|33
From Clock     : clk2
To Clock       : clk2
Failed Paths   : 10

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : tf_top:inst4|conter8:inst|74390:inst|33
To             : tf_top:inst4|conter8:inst|74390:inst|33
From Clock     : clk
To Clock       : clk
Failed Paths   : 8

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 18

--------------------------------------------------------------------------------------