allot.vhd

来自「基于FPGA的多波形发生器（编程环境QuartusII6.0）」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALLOT IS
	PORT(	s0,s1:IN STD_LOGIC;
	         n	:IN STD_LOGIC;
			a,b,c :OUT STD_LOGIC);
END;
ARCHITECTURE one OF allot IS
SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
S<=s0&s1;
PROCESS(S,n)
begin
a<='0';b<='0';c<='0';
CASE S IS
    WHEN "01"=> a<=n;
    WHEN "10"=> b<=n;
    WHEN "11"=> c<=n;
    WHEN OTHERS=>NULL;
  end case;
end process;
end one;