top.fit.eqn

基于FPGA的多波形发生器（编程环境QuartusII6.0）

N1_q_b[7]_PORT_B_data_in_reg = DFFE(N1_q_b[7]_PORT_B_data_in, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_write_enable = GND;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_write_enable = P1L92;
N1_q_b[7]_PORT_B_write_enable_reg = DFFE(N1_q_b[7]_PORT_B_write_enable, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_clock_0 = GLOBAL(clk);
N1_q_b[7]_clock_1 = GLOBAL(A1L5);
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, N1_q_b[7]_PORT_B_data_in_reg, N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_write_enable_reg, , , N1_q_b[7]_clock_0, N1_q_b[7]_clock_1, , , , );
N1_q_b[0] = N1_q_b[7]_PORT_B_data_out[7];

--N1_q_b[1] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_b[1] at M4K_X13_Y5
N1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_data_in = BUS(P1_ram_rom_data_reg[7], P1_ram_rom_data_reg[6], P1_ram_rom_data_reg[5], P1_ram_rom_data_reg[4], P1_ram_rom_data_reg[3], P1_ram_rom_data_reg[2], P1_ram_rom_data_reg[1], P1_ram_rom_data_reg[0]);
N1_q_b[7]_PORT_B_data_in_reg = DFFE(N1_q_b[7]_PORT_B_data_in, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_write_enable = GND;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_write_enable = P1L92;
N1_q_b[7]_PORT_B_write_enable_reg = DFFE(N1_q_b[7]_PORT_B_write_enable, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_clock_0 = GLOBAL(clk);
N1_q_b[7]_clock_1 = GLOBAL(A1L5);
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, N1_q_b[7]_PORT_B_data_in_reg, N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_write_enable_reg, , , N1_q_b[7]_clock_0, N1_q_b[7]_clock_1, , , , );
N1_q_b[1] = N1_q_b[7]_PORT_B_data_out[6];

--N1_q_b[2] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_b[2] at M4K_X13_Y5
N1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_data_in = BUS(P1_ram_rom_data_reg[7], P1_ram_rom_data_reg[6], P1_ram_rom_data_reg[5], P1_ram_rom_data_reg[4], P1_ram_rom_data_reg[3], P1_ram_rom_data_reg[2], P1_ram_rom_data_reg[1], P1_ram_rom_data_reg[0]);
N1_q_b[7]_PORT_B_data_in_reg = DFFE(N1_q_b[7]_PORT_B_data_in, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_write_enable = GND;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_write_enable = P1L92;
N1_q_b[7]_PORT_B_write_enable_reg = DFFE(N1_q_b[7]_PORT_B_write_enable, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_clock_0 = GLOBAL(clk);
N1_q_b[7]_clock_1 = GLOBAL(A1L5);
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, N1_q_b[7]_PORT_B_data_in_reg, N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_write_enable_reg, , , N1_q_b[7]_clock_0, N1_q_b[7]_clock_1, , , , );
N1_q_b[2] = N1_q_b[7]_PORT_B_data_out[5];

--N1_q_b[3] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_b[3] at M4K_X13_Y5
N1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_data_in = BUS(P1_ram_rom_data_reg[7], P1_ram_rom_data_reg[6], P1_ram_rom_data_reg[5], P1_ram_rom_data_reg[4], P1_ram_rom_data_reg[3], P1_ram_rom_data_reg[2], P1_ram_rom_data_reg[1], P1_ram_rom_data_reg[0]);
N1_q_b[7]_PORT_B_data_in_reg = DFFE(N1_q_b[7]_PORT_B_data_in, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_write_enable = GND;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_write_enable = P1L92;
N1_q_b[7]_PORT_B_write_enable_reg = DFFE(N1_q_b[7]_PORT_B_write_enable, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_clock_0 = GLOBAL(clk);
N1_q_b[7]_clock_1 = GLOBAL(A1L5);
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, N1_q_b[7]_PORT_B_data_in_reg, N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_write_enable_reg, , , N1_q_b[7]_clock_0, N1_q_b[7]_clock_1, , , , );
N1_q_b[3] = N1_q_b[7]_PORT_B_data_out[4];

--N1_q_b[4] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_b[4] at M4K_X13_Y5
N1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_data_in = BUS(P1_ram_rom_data_reg[7], P1_ram_rom_data_reg[6], P1_ram_rom_data_reg[5], P1_ram_rom_data_reg[4], P1_ram_rom_data_reg[3], P1_ram_rom_data_reg[2], P1_ram_rom_data_reg[1], P1_ram_rom_data_reg[0]);
N1_q_b[7]_PORT_B_data_in_reg = DFFE(N1_q_b[7]_PORT_B_data_in, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_write_enable = GND;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_write_enable = P1L92;
N1_q_b[7]_PORT_B_write_enable_reg = DFFE(N1_q_b[7]_PORT_B_write_enable, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_clock_0 = GLOBAL(clk);
N1_q_b[7]_clock_1 = GLOBAL(A1L5);
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, N1_q_b[7]_PORT_B_data_in_reg, N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_write_enable_reg, , , N1_q_b[7]_clock_0, N1_q_b[7]_clock_1, , , , );
N1_q_b[4] = N1_q_b[7]_PORT_B_data_out[3];

--N1_q_b[5] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_b[5] at M4K_X13_Y5
N1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_data_in = BUS(P1_ram_rom_data_reg[7], P1_ram_rom_data_reg[6], P1_ram_rom_data_reg[5], P1_ram_rom_data_reg[4], P1_ram_rom_data_reg[3], P1_ram_rom_data_reg[2], P1_ram_rom_data_reg[1], P1_ram_rom_data_reg[0]);
N1_q_b[7]_PORT_B_data_in_reg = DFFE(N1_q_b[7]_PORT_B_data_in, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_write_enable = GND;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_write_enable = P1L92;
N1_q_b[7]_PORT_B_write_enable_reg = DFFE(N1_q_b[7]_PORT_B_write_enable, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_clock_0 = GLOBAL(clk);
N1_q_b[7]_clock_1 = GLOBAL(A1L5);
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, N1_q_b[7]_PORT_B_data_in_reg, N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_write_enable_reg, , , N1_q_b[7]_clock_0, N1_q_b[7]_clock_1, , , , );
N1_q_b[5] = N1_q_b[7]_PORT_B_data_out[2];

--N1_q_b[6] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_b[6] at M4K_X13_Y5
N1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
N1_q_b[7]_PORT_A_data_in_reg = DFFE(N1_q_b[7]_PORT_A_data_in, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_data_in = BUS(P1_ram_rom_data_reg[7], P1_ram_rom_data_reg[6], P1_ram_rom_data_reg[5], P1_ram_rom_data_reg[4], P1_ram_rom_data_reg[3], P1_ram_rom_data_reg[2], P1_ram_rom_data_reg[1], P1_ram_rom_data_reg[0]);
N1_q_b[7]_PORT_B_data_in_reg = DFFE(N1_q_b[7]_PORT_B_data_in, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_address = BUS(K1_safe_q[0], K1_safe_q[1], K1_safe_q[2], K1_safe_q[3], K1_safe_q[4], K1_safe_q[5]);
N1_q_b[7]_PORT_A_address_reg = DFFE(N1_q_b[7]_PORT_A_address, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_address = BUS(R1_safe_q[0], R1_safe_q[1], R1_safe_q[2], R1_safe_q[3], R1_safe_q[4], R1_safe_q[5]);
N1_q_b[7]_PORT_B_address_reg = DFFE(N1_q_b[7]_PORT_B_address, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_PORT_A_write_enable = GND;
N1_q_b[7]_PORT_A_write_enable_reg = DFFE(N1_q_b[7]_PORT_A_write_enable, N1_q_b[7]_clock_0, , , );
N1_q_b[7]_PORT_B_write_enable = P1L92;
N1_q_b[7]_PORT_B_write_enable_reg = DFFE(N1_q_b[7]_PORT_B_write_enable, N1_q_b[7]_clock_1, , , );
N1_q_b[7]_clock_0 = GLOBAL(clk);
N1_q_b[7]_clock_1 = GLOBAL(A1L5);
N1_q_b[7]_PORT_B_data_out = MEMORY(N1_q_b[7]_PORT_A_data_in_reg, N1_q_b[7]_PORT_B_data_in_reg, N1_q_b[7]_PORT_A_address_reg, N1_q_b[7]_PORT_B_address_reg, N1_q_b[7]_PORT_A_write_enable_reg, N1_q_b[7]_PORT_B_write_enable_reg, , , N1_q_b[7]_clock_0, N1_q_b[7]_clock_1, , , , );
N1_q_b[6] = N1_q_b[7]_PORT_B_data_out[1];


--V1_q_a[7] is SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|altsyncram_bca2:altsyncram1|q_a[7] at M4K_X13_Y4
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[7]_PORT_A_data_in_reg = DFFE(V1_q_a[7]_PORT_A_data_in, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_PORT_B_data_in = BUS(P2_ram_rom_data_reg[7], P2_ram_rom_data_reg[6], P2_ram_rom_data_reg[5], P2_ram_rom_data_reg[4], P2_ram_rom_data_reg[3], P2_ram_rom_data_reg[2], P2_ram_rom_data_reg[1], P2_ram_rom_data_reg[0]);
V1_q_a[7]_PORT_B_data_in_reg = DFFE(V1_q_a[7]_PORT_B_data_in, V1_q_a[7]_clock_1, , , );
V1_q_a[7]_PORT_A_address = BUS(K2_safe_q[0], K2_safe_q[1], K2_safe_q[2], K2_safe_q[3], K2_safe_q[4], K2_safe_q[5]);
V1_q_a[7]_PORT_A_address_reg = DFFE(V1_q_a[7]_PORT_A_address, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_PORT_B_address = BUS(R2_safe_q[0], R2_safe_q[1], R2_safe_q[2], R2_safe_q[3], R2_safe_q[4], R2_safe_q[5]);
V1_q_a[7]_PORT_B_address_reg = DFFE(V1_q_a[7]_PORT_B_address, V1_q_a[7]_clock_1, , , );
V1_q_a[7]_PORT_A_write_enable = GND;
V1_q_a[7]_PORT_A_write_enable_reg = DFFE(V1_q_a[7]_PORT_A_write_enable, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_PORT_B_write_enable = P2L92;
V1_q_a[7]_PORT_B_write_enable_reg = DFFE(V1_q_a[7]_PORT_B_write_enable, V1_q_a[7]_clock_1, , , );
V1_q_a[7]_clock_0 = GLOBAL(clk);
V1_q_a[7]_clock_1 = GLOBAL(A1L5);
V1_q_a[7]_PORT_A_data_out = MEMORY(V1_q_a[7]_PORT_A_data_in_reg, V1_q_a[7]_PORT_B_data_in_reg, V1_q_a[7]_PORT_A_address_reg, V1_q_a[7]_PORT_B_address_reg, V1_q_a[7]_PORT_A_write_enable_reg, V1_q_a[7]_PORT_B_write_enable_reg, , , V1_q_a[7]_clock_0, V1_q_a[7]_clock_1, , , , );
V1_q_a[7] = V1_q_a[7]_PORT_A_data_out[0];

--V1_q_b[7] is SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|altsyncram_bca2:altsyncram1|q_b[7] at M4K_X13_Y4
V1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_b[7]_PORT_A_data_in_reg = DFFE(V1_q_b[7]_PORT_A_data_in, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_data_in = BUS(P2_ram_rom_data_reg[7], P2_ram_rom_data_reg[6], P2_ram_rom_data_reg[5], P2_ram_rom_data_reg[4], P2_ram_rom_data_reg[3], P2_ram_rom_data_reg[2], P2_ram_rom_data_reg[1], P2_ram_rom_data_reg[0]);
V1_q_b[7]_PORT_B_data_in_reg = DFFE(V1_q_b[7]_PORT_B_data_in, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_PORT_A_address = BUS(K2_safe_q[0], K2_safe_q[1], K2_safe_q[2], K2_safe_q[3], K2_safe_q[4], K2_safe_q[5]);
V1_q_b[7]_PORT_A_address_reg = DFFE(V1_q_b[7]_PORT_A_address, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_address = BUS(R2_safe_q[0], R2_safe_q[1], R2_safe_q[2], R2_safe_q[3], R2_safe_q[4], R2_safe_q[5]);
V1_q_b[7]_PORT_B_address_reg = DFFE(V1_q_b[7]_PORT_B_address, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_PORT_A_write_enable = GND;
V1_q_b[7]_PORT_A_write_enable_reg = DFFE(V1_q_b[7]_PORT_A_write_enable, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_write_enable = P2L92;
V1_q_b[7]_PORT_B_write_enable_reg = DFFE(V1_q_b[7]_PORT_B_write_enable, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_clock_0 = GLOBAL(clk);
V1_q_b[7]_clock_1 = GLOBAL(A1L5);
V1_q_b[7]_PORT_B_data_out = MEMORY(V1_q_b[7]_PORT_A_data_in_reg, V1_q_b[7]_PORT_B_data_in_reg, V1_q_b[7]_PORT_A_address_reg, V1_q_b[7]_PORT_B_address_reg, V1_q_b[7]_PORT_A_write_enable_reg, V1_q_b[7]_PORT_B_write_enable_reg, , , V1_q_b[7]_clock_0, V1_q_b[7]_clock_1, , , , );
V1_q_b[7] = V1_q_b[7]_PORT_B_data_out[0];

--V1_q_a[0] is SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|altsyncram_bca2:altsyncram1|q_a[0] at M4K_X13_Y4
V1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
V1_q_a[7]_PORT_A_data_in_reg = DFFE(V1_q_a[7]_PORT_A_data_in, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_PORT_B_data_in = BUS(P2_ram_rom_data_reg[7], P2_ram