top.fit.eqn

基于FPGA的多波形发生器（编程环境QuartusII6.0）

Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[4] = Y1_q_a[7]_PORT_A_data_out[3];

--Y1_q_a[5] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[5] at M4K_X13_Y6
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);
Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[5] = Y1_q_a[7]_PORT_A_data_out[2];

--Y1_q_a[6] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[6] at M4K_X13_Y6
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);
Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[6] = Y1_q_a[7]_PORT_A_data_out[1];

--Y1_q_b[0] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[0] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[0] = Y1_q_b[7]_PORT_B_data_out[7];

--Y1_q_b[1] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[1] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[1] = Y1_q_b[7]_PORT_B_data_out[6];

--Y1_q_b[2] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[2] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[2] = Y1_q_b[7]_PORT_B_data_out[5];

--Y1_q_b[3] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[3] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[3] = Y1_q_b[7]_PORT_B_data_out[4];

--Y1_q_b[4] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[4] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[4] = Y1_q_b[7]_PORT_B_data_out[3];

--Y1_q_b[5] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[5] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[5] = Y1_q_b[7]_PORT_B_data_out[2];

--Y1_q_b[6] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[6] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[6] = Y1_q_b[7]_PORT_B_data_out[1];


--N1_q_a[7] is SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1|q_a[7] at M4K_X13_Y5
--RAM Block Operation Mode: True Dual-Port