top.fit.eqn

基于FPGA的多波形发生器（编程环境QuartusII6.0）

--operation mode is normal

DB1_33_lut_out = !DB1_33;
DB1_33 = DFFEA(DB1_33_lut_out, DB1_29, !AB1L4, , , , );


--DB1_34 is tf_top:inst4|conter8:inst|74390:inst|34 at LC_X15_Y1_N4
--operation mode is normal

DB1_34_lut_out = !DB1_34;
DB1_34 = DFFEA(DB1_34_lut_out, Z1L1, !AB1L4, , , , );


--DB1_3 is tf_top:inst4|conter8:inst|74390:inst|3 at LC_X11_Y2_N2
--operation mode is normal

DB1_3_lut_out = DB1_5 & DB1_6 & !DB1_3;
DB1_3 = DFFEA(DB1_3_lut_out, !DB1_7, !AB1L4, , , , );


--DB1_5 is tf_top:inst4|conter8:inst|74390:inst|5 at LC_X10_Y2_N6
--operation mode is normal

DB1_5_lut_out = !DB1_5;
DB1_5 = DFFEA(DB1_5_lut_out, !DB1_6, !AB1L4, , , , );


--DB1_6 is tf_top:inst4|conter8:inst|74390:inst|6 at LC_X11_Y2_N8
--operation mode is normal

DB1_6_lut_out = !DB1_6;
DB1_6 = DFFEA(DB1_6_lut_out, DB1_20, !AB1L4, , , , );


--DB1_7 is tf_top:inst4|conter8:inst|74390:inst|7 at LC_X12_Y2_N8
--operation mode is normal

DB1_7_lut_out = !DB1_7;
DB1_7 = DFFEA(DB1_7_lut_out, Z1_inst2, !AB1L4, , , , );


--Y1_q_a[7] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[7] at M4K_X13_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);
Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[7] = Y1_q_a[7]_PORT_A_data_out[0];

--Y1_q_b[7] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_b[7] at M4K_X13_Y6
Y1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_b[7]_PORT_A_data_in_reg = DFFE(Y1_q_b[7]_PORT_A_data_in, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_b[7]_PORT_B_data_in_reg = DFFE(Y1_q_b[7]_PORT_B_data_in, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_b[7]_PORT_A_address_reg = DFFE(Y1_q_b[7]_PORT_A_address, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_b[7]_PORT_B_address_reg = DFFE(Y1_q_b[7]_PORT_B_address, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_PORT_A_write_enable = GND;
Y1_q_b[7]_PORT_A_write_enable_reg = DFFE(Y1_q_b[7]_PORT_A_write_enable, Y1_q_b[7]_clock_0, , , );
Y1_q_b[7]_PORT_B_write_enable = P3L92;
Y1_q_b[7]_PORT_B_write_enable_reg = DFFE(Y1_q_b[7]_PORT_B_write_enable, Y1_q_b[7]_clock_1, , , );
Y1_q_b[7]_clock_0 = GLOBAL(clk);
Y1_q_b[7]_clock_1 = GLOBAL(A1L5);
Y1_q_b[7]_PORT_B_data_out = MEMORY(Y1_q_b[7]_PORT_A_data_in_reg, Y1_q_b[7]_PORT_B_data_in_reg, Y1_q_b[7]_PORT_A_address_reg, Y1_q_b[7]_PORT_B_address_reg, Y1_q_b[7]_PORT_A_write_enable_reg, Y1_q_b[7]_PORT_B_write_enable_reg, , , Y1_q_b[7]_clock_0, Y1_q_b[7]_clock_1, , , , );
Y1_q_b[7] = Y1_q_b[7]_PORT_B_data_out[0];

--Y1_q_a[0] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[0] at M4K_X13_Y6
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);
Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[0] = Y1_q_a[7]_PORT_A_data_out[7];

--Y1_q_a[1] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[1] at M4K_X13_Y6
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);
Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[1] = Y1_q_a[7]_PORT_A_data_out[6];

--Y1_q_a[2] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[2] at M4K_X13_Y6
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);
Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[2] = Y1_q_a[7]_PORT_A_data_out[5];

--Y1_q_a[3] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[3] at M4K_X13_Y6
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);
Y1_q_a[7]_PORT_A_data_out = MEMORY(Y1_q_a[7]_PORT_A_data_in_reg, Y1_q_a[7]_PORT_B_data_in_reg, Y1_q_a[7]_PORT_A_address_reg, Y1_q_a[7]_PORT_B_address_reg, Y1_q_a[7]_PORT_A_write_enable_reg, Y1_q_a[7]_PORT_B_write_enable_reg, , , Y1_q_a[7]_clock_0, Y1_q_a[7]_clock_1, , , , );
Y1_q_a[3] = Y1_q_a[7]_PORT_A_data_out[4];

--Y1_q_a[4] is JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|altsyncram_p5a2:altsyncram1|q_a[4] at M4K_X13_Y6
Y1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
Y1_q_a[7]_PORT_A_data_in_reg = DFFE(Y1_q_a[7]_PORT_A_data_in, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_data_in = BUS(P3_ram_rom_data_reg[7], P3_ram_rom_data_reg[6], P3_ram_rom_data_reg[5], P3_ram_rom_data_reg[4], P3_ram_rom_data_reg[3], P3_ram_rom_data_reg[2], P3_ram_rom_data_reg[1], P3_ram_rom_data_reg[0]);
Y1_q_a[7]_PORT_B_data_in_reg = DFFE(Y1_q_a[7]_PORT_B_data_in, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_address = BUS(K3_safe_q[0], K3_safe_q[1], K3_safe_q[2], K3_safe_q[3], K3_safe_q[4], K3_safe_q[5]);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_address = BUS(R3_safe_q[0], R3_safe_q[1], R3_safe_q[2], R3_safe_q[3], R3_safe_q[4], R3_safe_q[5]);
Y1_q_a[7]_PORT_B_address_reg = DFFE(Y1_q_a[7]_PORT_B_address, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_PORT_A_write_enable = GND;
Y1_q_a[7]_PORT_A_write_enable_reg = DFFE(Y1_q_a[7]_PORT_A_write_enable, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_PORT_B_write_enable = P3L92;
Y1_q_a[7]_PORT_B_write_enable_reg = DFFE(Y1_q_a[7]_PORT_B_write_enable, Y1_q_a[7]_clock_1, , , );
Y1_q_a[7]_clock_0 = GLOBAL(clk);
Y1_q_a[7]_clock_1 = GLOBAL(A1L5);