mux41a.vhd

基于FPGA的多波形发生器（编程环境QuartusII6.0）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX41A IS
	PORT(	s0,s1:IN STD_LOGIC;
	         A,B,C	:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			DATAOUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE one OF MUX41A IS
SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
S<=s0&s1;
PROCESS(S,A,B,C)
begin
CASE S IS
    WHEN "01"=> DATAOUT<=A;
    WHEN "10"=> DATAOUT<=B;
    WHEN "11"=> DATAOUT<=C;
    WHEN OTHERS=>NULL;
  end case;
end process;
end one;