top.map.rpt

基于FPGA的多波形发生器（编程环境QuartusII6.0）

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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jun 19 17:25:17 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off top -c top
Info: Found 2 design units, including 1 entities, in source file SINCRT.vhd
    Info: Found design unit 1: SINCRT-DACC
    Info: Found entity 1: SINCRT
Info: Found 2 design units, including 1 entities, in source file SJCRT.vhd
    Info: Found design unit 1: SJCRT-DACC
    Info: Found entity 1: SJCRT
Info: Found 2 design units, including 1 entities, in source file JCCRT.vhd
    Info: Found design unit 1: JCCRT-DACC
    Info: Found entity 1: JCCRT
Info: Found 2 design units, including 1 entities, in source file ALLOT.vhd
    Info: Found design unit 1: ALLOT-one
    Info: Found entity 1: ALLOT
Info: Found 1 design units, including 1 entities, in source file top.bdf
    Info: Found entity 1: top
Info: Found 2 design units, including 1 entities, in source file MUX41A.vhd
    Info: Found design unit 1: MUX41A-one
    Info: Found entity 1: MUX41A
Info: Found 2 design units, including 1 entities, in source file data_rom1.vhd
    Info: Found design unit 1: data_rom1-SYN
    Info: Found entity 1: data_rom1
Info: Found 2 design units, including 1 entities, in source file data_rom2.vhd
    Info: Found design unit 1: data_rom2-SYN
    Info: Found entity 1: data_rom2
Info: Found 2 design units, including 1 entities, in source file data_rom3.vhd
    Info: Found design unit 1: data_rom3-SYN
    Info: Found entity 1: data_rom3
Info: Using design file h:/ѧϰ/eda/shiyan2/shi yan er/tf_top.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: tf_top
Warning: Block or symbol conter8 of instance inst overlaps another block or symbol
Info: Using design file h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: conter8
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/others/maxplus2/74390.bdf
    Info: Found entity 1: 74390
Info: Using design file h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: tf_ctro
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/others/maxplus2/7493.bdf
    Info: Found entity 1: 7493
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/others/maxplus2/74154.bdf
    Info: Found entity 1: 74154
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/others/maxplus2/74248.bdf
    Info: Found entity 1: 74248
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/others/maxplus2/74374.bdf
    Info: Found entity 1: 74374
Warning: VHDL Process Statement warning at MUX41A.vhd(13): signal or variable dataout may not be assigned a new value in every possible path through the Process Statement. Signal or variable dataout holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_q8s.tdf
    Info: Found entity 1: altsyncram_q8s
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gv92.tdf
    Info: Found entity 1: altsyncram_gv92
Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mls.tdf
    Info: Found entity 1: altsyncram_mls
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bca2.tdf
    Info: Found entity 1: altsyncram_bca2
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5fs.tdf
    Info: Found entity 1: altsyncram_5fs
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_p5a2.tdf
    Info: Found entity 1: altsyncram_p5a2
Info: Found 6 design units, including 2 entities, in source file c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf
    Info: Found entity 1: decode_9ie
Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Ignored 8 buffer(s)
    Info: Ignored 8 SOFT buffer(s)
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: JCCRT:inst2|Q1[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: SJCRT:inst1|Q1[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: SINCRT:inst|Q1[0]~0
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~240
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~8
Info: Inferred 2 megafunctions from design logic
    Info: Inferred l