📄 top.map.rpt
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; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+--------------------------------------------------------------------+--------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |top|MUX41A:inst3|Mux~0 ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 22:1 ; 4 bits ; 56 LEs ; 48 LEs ; 8 LEs ; Yes ; |top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |top|SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |top|SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |top|SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 22:1 ; 4 bits ; 56 LEs ; 48 LEs ; 8 LEs ; Yes ; |top|SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |top|JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |top|JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |top|JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 22:1 ; 4 bits ; 56 LEs ; 44 LEs ; 12 LEs ; Yes ; |top|JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 15 bits ; 15 LEs ; 15 LEs ; 0 LEs ; Yes ; |top|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] ;
; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; Yes ; |top|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] ;
; 34:1 ; 4 bits ; 88 LEs ; 40 LEs ; 48 LEs ; Yes ; |top|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1] ;
; 2:1 ; 3 bits ; 3 LEs ; 3 LEs ; 0 LEs ; No ; |top|sld_hub:sld_hub_inst|NODE_ENA~2 ;
; 2:1 ; 3 bits ; 3 LEs ; 3 LEs ; 0 LEs ; No ; |top|sld_hub:sld_hub_inst|SHADOW_IRF_ENABLE[3] ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |top|sld_hub:sld_hub_inst|IR_MUX_SEL[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 115 ;
; Number of synthesis-generated cells ; 317 ;
; Number of WYSIWYG LUTs ; 115 ;
; Number of synthesis-generated LUTs ; 241 ;
; Number of WYSIWYG registers ; 84 ;
; Number of synthesis-generated registers ; 149 ;
; Number of cells with combinational logic only ; 199 ;
; Number of cells with registers only ; 76 ;
; Number of cells with combinational logic and registers ; 157 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear ; 12 ;
; Number of registers using Synchronous Load ; 54 ;
; Number of registers using Asynchronous Clear ; 154 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 116 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Setting ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode ; Hierarchy Location ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------------------+
; 0 ; rom1 ; 8 ; 64 ; Read/Write ; |top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated ;
; 1 ; rom2 ; 8 ; 64 ; Read/Write ; |top|SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated ;
; 2 ; rom3 ; 8 ; 64 ; Read/Write ; |top|JCCRT:inst2|data_rom3:u1|altsyncram:altsyncram_component|altsyncram_5fs:auto_generated ;
+----------------+-------------+-------+-------+------------+---------------------------------------------------------------------------------------------+
+-----------+
; Hierarchy ;
+-----------+
top
|-- SINCRT:inst
|-- lpm_counter:Q1_rtl_2
|-- cntr_es6:auto_generated
|-- data_rom1:u1
|-- altsyncram:altsyncram_component
|-- altsyncram_q8s:auto_generated
|-- altsyncram_gv92:altsyncram1
|-- sld_mod_ram_rom:mgl_prim2
|-- sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
|-- lpm_counter:ram_rom_addr_reg_rtl_0
|-- cntr_t98:auto_generated
|-- lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1
|-- cntr_pd8:auto_generated
|-- SJCRT:inst1
|-- lpm_counter:Q1_rtl_1
|-- cntr_es6:auto_generated
|-- data_rom2:u1
|-- altsyncram:altsyncram_component
|-- altsyncram_mls:auto_generated
|-- altsyncram_bca2:altsyncram1
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