ii2cn1.map.qmsg

来自「verilog在cpld上实现i2c主从设备通讯功能」· QMSG 代码 · 共 14 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 18 17:13:59 2007 " "Info: Processing started: Sun Nov 18 17:13:59 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ii2cn1 -c ii2cn1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ii2cn1 -c ii2cn1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_master_bit_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_master_bit_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_master_bit_ctrl " "Info: Found entity 1: i2c_master_bit_ctrl" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_master_byte_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_master_byte_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_master_byte_ctrl " "Info: Found entity 1: i2c_master_byte_ctrl" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_master_defines.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file i2c_master_defines.v" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_master_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_master_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_master_top " "Info: Found entity 1: i2c_master_top" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_slave_model.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_slave_model.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_slave_model " "Info: Found entity 1: i2c_slave_model" {  } { { "i2c_slave_model.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_slave_model.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timescale.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file timescale.v" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tst_bench_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file tst_bench_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 tst_bench_top " "Info: Found entity 1: tst_bench_top" {  } { { "tst_bench_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/tst_bench_top.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "wb_master_model.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file wb_master_model.v" { { "Info" "ISGN_ENTITY_NAME" "1 wb_master_model " "Info: Found entity 1: wb_master_model" {  } { { "wb_master_model.v" "" { Text "D:/My Docu/CPLD/i2c Sample/wb_master_model.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "ii2cn1 " "Error: Top-level design entity \"ii2cn1\" is undefined" {  } {  } 0 0 "Top-level design entity \"%1!s!\" is undefined" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sun Nov 18 17:14:00 2007 " "Error: Processing ended: Sun Nov 18 17:14:00 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}