i2c_master_top.tan.qmsg

来自「verilog在cpld上实现i2c主从设备通讯功能」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "wb_clk_i register cr\[5\] register i2c_master_byte_ctrl:byte_controller\|core_cmd\[3\] 183.18 MHz 5.459 ns Internal " "Info: Clock \"wb_clk_i\" has Internal fmax of 183.18 MHz between source register \"cr\[5\]\" and destination register \"i2c_master_byte_ctrl:byte_controller\|core_cmd\[3\]\" (period= 5.459 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.185 ns + Longest register register " "Info: + Longest register to register delay is 5.185 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cr\[5\] 1 REG LC_X34_Y19_N8 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y19_N8; Fanout = 8; REG Node = 'cr\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { cr[5] } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.299 ns) + CELL(0.366 ns) 1.665 ns i2c_master_byte_ctrl:byte_controller\|go~44 2 COMB LC_X35_Y18_N4 7 " "Info: 2: + IC(1.299 ns) + CELL(0.366 ns) = 1.665 ns; Loc. = LC_X35_Y18_N4; Fanout = 7; COMB Node = 'i2c_master_byte_ctrl:byte_controller\|go~44'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "1.665 ns" { cr[5] i2c_master_byte_ctrl:byte_controller|go~44 } "NODE_NAME" } "" } } { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.280 ns) 3.190 ns i2c_master_byte_ctrl:byte_controller\|core_cmd~1555 3 COMB LC_X34_Y21_N1 2 " "Info: 3: + IC(1.245 ns) + CELL(0.280 ns) = 3.190 ns; Loc. = LC_X34_Y21_N1; Fanout = 2; COMB Node = 'i2c_master_byte_ctrl:byte_controller\|core_cmd~1555'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "1.525 ns" { i2c_master_byte_ctrl:byte_controller|go~44 i2c_master_byte_ctrl:byte_controller|core_cmd~1555 } "NODE_NAME" } "" } } { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.290 ns) + CELL(0.705 ns) 5.185 ns i2c_master_byte_ctrl:byte_controller\|core_cmd\[3\] 4 REG LC_X33_Y20_N5 6 " "Info: 4: + IC(1.290 ns) + CELL(0.705 ns) = 5.185 ns; Loc. = LC_X33_Y20_N5; Fanout = 6; REG Node = 'i2c_master_byte_ctrl:byte_controller\|core_cmd\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "1.995 ns" { i2c_master_byte_ctrl:byte_controller|core_cmd~1555 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } "NODE_NAME" } "" } } { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.351 ns ( 26.06 % ) " "Info: Total cell delay = 1.351 ns ( 26.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.834 ns ( 73.94 % ) " "Info: Total interconnect delay = 3.834 ns ( 73.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "5.185 ns" { cr[5] i2c_master_byte_ctrl:byte_controller|go~44 i2c_master_byte_ctrl:byte_controller|core_cmd~1555 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.185 ns" { cr[5] i2c_master_byte_ctrl:byte_controller|go~44 i2c_master_byte_ctrl:byte_controller|core_cmd~1555 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } { 0.000ns 1.299ns 1.245ns 1.290ns } { 0.000ns 0.366ns 0.280ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.108 ns - Smallest " "Info: - Smallest clock skew is -0.108 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_clk_i destination 2.792 ns + Shortest register " "Info: + Shortest clock path from clock \"wb_clk_i\" to destination register is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns wb_clk_i 1 CLK PIN_L2 131 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 131; CLK Node = 'wb_clk_i'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_clk_i } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.525 ns) + CELL(0.542 ns) 2.792 ns i2c_master_byte_ctrl:byte_controller\|core_cmd\[3\] 2 REG LC_X33_Y20_N5 6 " "Info: 2: + IC(1.525 ns) + CELL(0.542 ns) = 2.792 ns; Loc. = LC_X33_Y20_N5; Fanout = 6; REG Node = 'i2c_master_byte_ctrl:byte_controller\|core_cmd\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.067 ns" { wb_clk_i i2c_master_byte_ctrl:byte_controller|core_cmd[3] } "NODE_NAME" } "" } } { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.38 % ) " "Info: Total cell delay = 1.267 ns ( 45.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.525 ns ( 54.62 % ) " "Info: Total interconnect delay = 1.525 ns ( 54.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.792 ns" { wb_clk_i i2c_master_byte_ctrl:byte_controller|core_cmd[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { wb_clk_i wb_clk_i~out0 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } { 0.000ns 0.000ns 1.525ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_clk_i source 2.900 ns - Longest register " "Info: - Longest clock path from clock \"wb_clk_i\" to source register is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns wb_clk_i 1 CLK PIN_L2 131 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 131; CLK Node = 'wb_clk_i'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_clk_i } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(0.542 ns) 2.900 ns cr\[5\] 2 REG LC_X34_Y19_N8 8 " "Info: 2: + IC(1.633 ns) + CELL(0.542 ns) = 2.900 ns; Loc. = LC_X34_Y19_N8; Fanout = 8; REG Node = 'cr\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.175 ns" { wb_clk_i cr[5] } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.69 % ) " "Info: Total cell delay = 1.267 ns ( 43.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.633 ns ( 56.31 % ) " "Info: Total interconnect delay = 1.633 ns ( 56.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.900 ns" { wb_clk_i cr[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.900 ns" { wb_clk_i wb_clk_i~out0 cr[5] } { 0.000ns 0.000ns 1.633ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.792 ns" { wb_clk_i i2c_master_byte_ctrl:byte_controller|core_cmd[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { wb_clk_i wb_clk_i~out0 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } { 0.000ns 0.000ns 1.525ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.900 ns" { wb_clk_i cr[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.900 ns" { wb_clk_i wb_clk_i~out0 cr[5] } { 0.000ns 0.000ns 1.633ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 136 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "5.185 ns" { cr[5] i2c_master_byte_ctrl:byte_controller|go~44 i2c_master_byte_ctrl:byte_controller|core_cmd~1555 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.185 ns" { cr[5] i2c_master_byte_ctrl:byte_controller|go~44 i2c_master_byte_ctrl:byte_controller|core_cmd~1555 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } { 0.000ns 1.299ns 1.245ns 1.290ns } { 0.000ns 0.366ns 0.280ns 0.705ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.792 ns" { wb_clk_i i2c_master_byte_ctrl:byte_controller|core_cmd[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { wb_clk_i wb_clk_i~out0 i2c_master_byte_ctrl:byte_controller|core_cmd[3] } { 0.000ns 0.000ns 1.525ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.900 ns" { wb_clk_i cr[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.900 ns" { wb_clk_i wb_clk_i~out0 cr[5] } { 0.000ns 0.000ns 1.633ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "cr\[6\] wb_cyc_i wb_clk_i 6.700 ns register " "Info: tsu for register \"cr\[6\]\" (data pin = \"wb_cyc_i\", clock pin = \"wb_clk_i\") is 6.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.482 ns + Longest pin register " "Info: + Longest pin to register delay is 9.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns wb_cyc_i 1 PIN PIN_U9 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U9; Fanout = 4; PIN Node = 'wb_cyc_i'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_cyc_i } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.160 ns) + CELL(0.183 ns) 5.430 ns wb_wacc 2 COMB LC_X36_Y16_N5 9 " "Info: 2: + IC(4.160 ns) + CELL(0.183 ns) = 5.430 ns; Loc. = LC_X36_Y16_N5; Fanout = 9; COMB Node = 'wb_wacc'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "4.343 ns" { wb_cyc_i wb_wacc } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.183 ns) 6.678 ns cr\[7\]~461 3 COMB LC_X36_Y19_N3 1 " "Info: 3: + IC(1.065 ns) + CELL(0.183 ns) = 6.678 ns; Loc. = LC_X36_Y19_N3; Fanout = 1; COMB Node = 'cr\[7\]~461'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "1.248 ns" { wb_wacc cr[7]~461 } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.798 ns) + CELL(0.075 ns) 7.551 ns cr\[7\]~462 4 COMB LC_X34_Y19_N0 4 " "Info: 4: + IC(0.798 ns) + CELL(0.075 ns) = 7.551 ns; Loc. = LC_X34_Y19_N0; Fanout = 4; COMB Node = 'cr\[7\]~462'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "0.873 ns" { cr[7]~461 cr[7]~462 } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.705 ns) 9.482 ns cr\[6\] 5 REG LC_X34_Y20_N4 4 " "Info: 5: + IC(1.226 ns) + CELL(0.705 ns) = 9.482 ns; Loc. = LC_X34_Y20_N4; Fanout = 4; REG Node = 'cr\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "1.931 ns" { cr[7]~462 cr[6] } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.233 ns ( 23.55 % ) " "Info: Total cell delay = 2.233 ns ( 23.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.249 ns ( 76.45 % ) " "Info: Total interconnect delay = 7.249 ns ( 76.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "9.482 ns" { wb_cyc_i wb_wacc cr[7]~461 cr[7]~462 cr[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.482 ns" { wb_cyc_i wb_cyc_i~out0 wb_wacc cr[7]~461 cr[7]~462 cr[6] } { 0.000ns 0.000ns 4.160ns 1.065ns 0.798ns 1.226ns } { 0.000ns 1.087ns 0.183ns 0.183ns 0.075ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_clk_i destination 2.792 ns - Shortest register " "Info: - Shortest clock path from clock \"wb_clk_i\" to destination register is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns wb_clk_i 1 CLK PIN_L2 131 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 131; CLK Node = 'wb_clk_i'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_clk_i } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.525 ns) + CELL(0.542 ns) 2.792 ns cr\[6\] 2 REG LC_X34_Y20_N4 4 " "Info: 2: + IC(1.525 ns) + CELL(0.542 ns) = 2.792 ns; Loc. = LC_X34_Y20_N4; Fanout = 4; REG Node = 'cr\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.067 ns" { wb_clk_i cr[6] } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.38 % ) " "Info: Total cell delay = 1.267 ns ( 45.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.525 ns ( 54.62 % ) " "Info: Total interconnect delay = 1.525 ns ( 54.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.792 ns" { wb_clk_i cr[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { wb_clk_i wb_clk_i~out0 cr[6] } { 0.000ns 0.000ns 1.525ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "9.482 ns" { wb_cyc_i wb_wacc cr[7]~461 cr[7]~462 cr[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.482 ns" { wb_cyc_i wb_cyc_i~out0 wb_wacc cr[7]~461 cr[7]~462 cr[6] } { 0.000ns 0.000ns 4.160ns 1.065ns 0.798ns 1.226ns } { 0.000ns 1.087ns 0.183ns 0.183ns 0.075ns 0.705ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.792 ns" { wb_clk_i cr[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { wb_clk_i wb_clk_i~out0 cr[6] } { 0.000ns 0.000ns 1.525ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "wb_clk_i wb_dat_o\[2\] wb_dat_o\[2\]~reg0 7.614 ns register " "Info: tco from clock \"wb_clk_i\" to destination pin \"wb_dat_o\[2\]\" through register \"wb_dat_o\[2\]~reg0\" is 7.614 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_clk_i source 2.789 ns + Longest register " "Info: + Longest clock path from clock \"wb_clk_i\" to source register is 2.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns wb_clk_i 1 CLK PIN_L2 131 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 131; CLK Node = 'wb_clk_i'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_clk_i } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.522 ns) + CELL(0.542 ns) 2.789 ns wb_dat_o\[2\]~reg0 2 REG LC_X35_Y21_N8 1 " "Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X35_Y21_N8; Fanout = 1; REG Node = 'wb_dat_o\[2\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.064 ns" { wb_clk_i wb_dat_o[2]~reg0 } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.43 % ) " "Info: Total cell delay = 1.267 ns ( 45.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.522 ns ( 54.57 % ) " "Info: Total interconnect delay = 1.522 ns ( 54.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.789 ns" { wb_clk_i wb_dat_o[2]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.789 ns" { wb_clk_i wb_clk_i~out0 wb_dat_o[2]~reg0 } { 0.000ns 0.000ns 1.522ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 104 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.669 ns + Longest register pin " "Info: + Longest register to pin delay is 4.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wb_dat_o\[2\]~reg0 1 REG LC_X35_Y21_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y21_N8; Fanout = 1; REG Node = 'wb_dat_o\[2\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_dat_o[2]~reg0 } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.265 ns) + CELL(2.404 ns) 4.669 ns wb_dat_o\[2\] 2 PIN PIN_V9 0 " "Info: 2: + IC(2.265 ns) + CELL(2.404 ns) = 4.669 ns; Loc. = PIN_V9; Fanout = 0; PIN Node = 'wb_dat_o\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "4.669 ns" { wb_dat_o[2]~reg0 wb_dat_o[2] } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 51.49 % ) " "Info: Total cell delay = 2.404 ns ( 51.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.265 ns ( 48.51 % ) " "Info: Total interconnect delay = 2.265 ns ( 48.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "4.669 ns" { wb_dat_o[2]~reg0 wb_dat_o[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.669 ns" { wb_dat_o[2]~reg0 wb_dat_o[2] } { 0.000ns 2.265ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.789 ns" { wb_clk_i wb_dat_o[2]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.789 ns" { wb_clk_i wb_clk_i~out0 wb_dat_o[2]~reg0 } { 0.000ns 0.000ns 1.522ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "4.669 ns" { wb_dat_o[2]~reg0 wb_dat_o[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.669 ns" { wb_dat_o[2]~reg0 wb_dat_o[2] } { 0.000ns 2.265ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "wb_ack_o~reg0 wb_stb_i wb_clk_i -2.105 ns register " "Info: th for register \"wb_ack_o~reg0\" (data pin = \"wb_stb_i\", clock pin = \"wb_clk_i\") is -2.105 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_clk_i destination 2.892 ns + Longest register " "Info: + Longest clock path from clock \"wb_clk_i\" to destination register is 2.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns wb_clk_i 1 CLK PIN_L2 131 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 131; CLK Node = 'wb_clk_i'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_clk_i } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.542 ns) 2.892 ns wb_ack_o~reg0 2 REG LC_X36_Y16_N4 2 " "Info: 2: + IC(1.625 ns) + CELL(0.542 ns) = 2.892 ns; Loc. = LC_X36_Y16_N4; Fanout = 2; REG Node = 'wb_ack_o~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.167 ns" { wb_clk_i wb_ack_o~reg0 } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.81 % ) " "Info: Total cell delay = 1.267 ns ( 43.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.625 ns ( 56.19 % ) " "Info: Total interconnect delay = 1.625 ns ( 56.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.892 ns" { wb_clk_i wb_ack_o~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.892 ns" { wb_clk_i wb_clk_i~out0 wb_ack_o~reg0 } { 0.000ns 0.000ns 1.625ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 89 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.097 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns wb_stb_i 1 PIN PIN_M2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 4; PIN Node = 'wb_stb_i'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "" { wb_stb_i } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.149 ns) + CELL(0.223 ns) 5.097 ns wb_ack_o~reg0 2 REG LC_X36_Y16_N4 2 " "Info: 2: + IC(4.149 ns) + CELL(0.223 ns) = 5.097 ns; Loc. = LC_X36_Y16_N4; Fanout = 2; REG Node = 'wb_ack_o~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "4.372 ns" { wb_stb_i wb_ack_o~reg0 } "NODE_NAME" } "" } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 18.60 % ) " "Info: Total cell delay = 0.948 ns ( 18.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.149 ns ( 81.40 % ) " "Info: Total interconnect delay = 4.149 ns ( 81.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "5.097 ns" { wb_stb_i wb_ack_o~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.097 ns" { wb_stb_i wb_stb_i~out0 wb_ack_o~reg0 } { 0.000ns 0.000ns 4.149ns } { 0.000ns 0.725ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "2.892 ns" { wb_clk_i wb_ack_o~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.892 ns" { wb_clk_i wb_clk_i~out0 wb_ack_o~reg0 } { 0.000ns 0.000ns 1.625ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c_master_top" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c Sample/db/i2c_master_top.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c Sample/" "" "5.097 ns" { wb_stb_i wb_ack_o~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.097 ns" { wb_stb_i wb_stb_i~out0 wb_ack_o~reg0 } { 0.000ns 0.000ns 4.149ns } { 0.000ns 0.725ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}