fulladder_4.map.summary

来自「浙江大学的VHDL中文教程」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Mon Nov 26 10:45:56 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : FullAdder_4
Top-level Entity Name : FullAdder_4
Family : FLEX10K
Total logic elements : 8
Total pins : 14
Total memory bits : 0