light_controller.v

来自「里面是一和始终的控制语言和怎么样实现的 对于用时钟控制FIR滤波器的 可以」· Verilog 代码 · 共 104 行

//======================================================================//
//
//Copyright(c)2001-2004 SIA. All rights reserved.
//
//THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF SIA.
//This program is the Confidential and Proprietary product of SIA
//Any unauthorized use,reproduction or transfer of this program is strictly prohibited.
//======================================================================//
//
//File        : light_controller.v
//Author      : Wenjie Cai
//Email       :  
//Tel         : [phone]
//Date        : 2004-11-11
//Version     :   1.0
//Description : traffic controller, timing red/green/yellow ligt.

//Amendment History
//   Date          By       Version   Change Description
//
// 2005/07/25      Mapq      1.0     initial versoin
//======================================================================//
`timescale 1s/1s

module light_controller(
                    sid,
                    prst_n,
                    red_on,
                    yellow_on,
                    green_on,
                    sod,
                    clk,  
                    rst_n
                    );
//parameter define
//IO  declaration   
input  sid;       //input serial data
input  prst_n;    //preset signal
output red_on;    //ligt on red indication
output green_on;  //ligt on green indication
output yellow_on; //ligt on yellow indication
output sod;       //input serial data
input  clk;       //clock, 1hz
input  rst_n;     //asynch reset,active low

wire sid;       //input serial data
wire prst_n;    //preset signal
wire red_on;    //ligt on red indication
wire green_on;  //ligt on green indication
wire yellow_on; //ligt on yellow indication
wire sod;       //input serial data
wire clk;       //clock, 1hz
wire rst_n;     //asynch reset,active low

//
wire prst ;
wire[7:0] red_counter, green_counter , yellow_counter ;
//
  light_config  light_config (
      .sid            ( sid            ),    // I 
      .sod            ( sod            ),    // O 
      .prst_n         ( prst_n         ),    // I 
      .red_counter    ( red_counter    ),    // O [CNT_LNG-1:0]
      .green_counter  ( green_counter  ),    // O [CNT_LNG-1:0]
      .yellow_counter ( yellow_counter ),    // O [CNT_LNG-1:0]
      .prst           ( prst           ),    // O 
      .clk            ( clk            ),    // I 
      .rst_n          ( rst_n          ) );  // I 
//
wire red_cleared , yellow_cleared , green_cleared ;
wire red_expired , yellow_expired , green_expired ;
//
  light_timing  light_timing (
      .red_cleared    ( red_cleared    ),    // I 
      .red_expired    ( red_expired    ),    // O 
      .red_counter    ( red_counter    ),    // I [CNT_LNG-1:0]
      .yellow_cleared ( yellow_cleared ),    // I 
      .yellow_expired ( yellow_expired ),    // O 
      .yellow_counter ( yellow_counter ),    // I [CNT_LNG-1:0]
      .green_cleared  ( green_cleared  ),    // I 
      .green_expired  ( green_expired  ),    // O 
      .green_counter  ( green_counter  ),    // I [CNT_LNG-1:0]
      .clk            ( clk            ),    // I 
      .rst_n          ( rst_n          ) );  // I 

// 
  light_fsm  light_fsm (
      .red_cleared    ( red_cleared    ),    // O 
      .red_expired    ( red_expired    ),    // I 
      .yellow_cleared ( yellow_cleared ),    // O 
      .yellow_expired ( yellow_expired ),    // I 
      .green_cleared  ( green_cleared  ),    // O 
      .green_expired  ( green_expired  ),    // I 
      .hold_on        ( prst           ),    // I 
      .red_ligt_on    ( red_on         ),    // O 
      .yellow_ligt_on ( yellow_on      ),    // O 
      .green_ligt_on  ( green_on       ),    // O 
      .clk            ( clk            ),    // I 
      .rst_n          ( rst_n          ) );  // I 
        
endmodule