i2c_tb.v

I2C 控制器的 Verilog源程序 example

//----------------------------------------------------------------------------
// 
//  Name:  i2c_tb.v   
// 
//  Description: Top-level test fixture for I2C serial controller
// 
//  $Revision: 1.0 $          
//  
//  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//
//----------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
//    5555 NE Moore Court
//    Hillsboro, OR 97124
//    U.S.A
//
//    TEL: 1-800-Lattice (USA and Canada)
//    408-826-6000 (other locations)
//
//    web: http://www.latticesemi.com/
//    email: [e-mail]
// 
//----------------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
Module  i2c
This is the top level test bench module for the Serial EEPROM
I2c Controller. 
*/

module i2c_tb();

wire    [7:0]   data;
wire    [1:0]   addr;
wire            rst_l;
wire            clock;
wire            cs_l;
wire            ack_l;
wire            rd_wr_l;

tri1            sda_pin;
tri1            scl_pin;

i2c I2C(        .data(data),               
                .addr(addr),
                .rst_l(rst_l),
                .clock(clock),
                .cs_l(cs_l),
                .ack_l(ack_l),
                .rd_wr_l(rd_wr_l),
                
                .reg_clk_in(pt_clk),
                
                .reg_clk_out(pt_clk),
                .scl_pin(scl_pin),
                .sda_pin(sda_pin));

clk_rst CLK(    .clk(clock),
                .rst_l(rst_l));
                
micro MICRO(    .clk(clock),
                .rst_l(rst_l),
                .data(data),              
                .addr(addr),
                .cs_l(cs_l),
                .ack_l(ack_l),
                .rd_wr_l(rd_wr_l));
                
i2c_slave SEP(  .sda(sda_pin),
                .scl(scl_pin));
                                
endmodule

//------------------------------- E O F --------------------------------------