traffic_control.rpt

假设某个十字路口是由一条主干道和一条次干道汇合而成

-- Equation name is 'N1', type is output 
N1       =  STATE0;

-- Node name is 'N2' 
-- Equation name is 'N2', type is output 
N2       =  _LC1_A4;

-- Node name is 'N3' 
-- Equation name is 'N3', type is output 
N3       =  _LC3_A1;

-- Node name is 'N4' 
-- Equation name is 'N4', type is output 
N4       =  _LC6_A3;

-- Node name is 'N5' 
-- Equation name is 'N5', type is output 
N5       = !_LC5_A1;

-- Node name is ':19' = 'STATE0' 
-- Equation name is 'STATE0', location is LC3_A2, type is buried.
STATE0   = DFFE( _EQ001, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ001 =  _LC2_A2 & !_LC5_A2
         #  _LC5_A2 &  M4 & !M5;

-- Node name is '~18~1' = 'STATE1~1' 
-- Equation name is '~18~1', location is LC7_A1, type is buried.
-- synthesized logic cell 
_LC7_A1  = DFFE( _EQ002, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ002 =  _LC2_A1 & !_LC7_A1 &  STATE0
         #  _LC7_A1 & !STATE0
         # !_LC4_A1 &  _LC7_A1;

-- Node name is '~18~2' = 'STATE1~2' 
-- Equation name is '~18~2', location is LC5_A1, type is buried.
-- synthesized logic cell 
_LC5_A1  = DFFE( _EQ003, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ003 =  _LC2_A1 & !_LC5_A1 &  STATE0
         #  _LC5_A1 & !STATE0
         # !_LC4_A1 &  _LC5_A1;

-- Node name is '~18~3' = 'STATE1~3' 
-- Equation name is '~18~3', location is LC3_A1, type is buried.
-- synthesized logic cell 
_LC3_A1  = DFFE( _EQ004, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ004 =  _LC2_A1 & !_LC3_A1 &  STATE0
         #  _LC3_A1 & !STATE0
         #  _LC3_A1 & !_LC4_A1;

-- Node name is ':18' = 'STATE1' 
-- Equation name is 'STATE1', location is LC1_A1, type is buried.
STATE1   = DFFE( _EQ005, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ005 =  _LC2_A1 &  STATE0 & !STATE1
         # !STATE0 &  STATE1
         # !_LC4_A1 &  STATE1;

-- Node name is ':72' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ006);
  _EQ006 =  M1 &  M5;

-- Node name is ':137' 
-- Equation name is '_LC4_A1', type is buried 
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ007);
  _EQ007 = !M1
         # !M3;

-- Node name is '~167~1' 
-- Equation name is '~167~1', location is LC1_A4, type is buried.
-- synthesized logic cell 
_LC1_A4  = LCELL( _EQ008);
  _EQ008 = !STATE0 &  STATE1;

-- Node name is ':167' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ009);
  _EQ009 = !STATE0 &  STATE1;

-- Node name is ':175' 
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = LCELL( _EQ010);
  _EQ010 =  STATE0 & !STATE1;

-- Node name is '~183~1' 
-- Equation name is '~183~1', location is LC6_A3, type is buried.
-- synthesized logic cell 
_LC6_A3  = LCELL( _EQ011);
  _EQ011 = !STATE0 & !STATE1;

-- Node name is ':183' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ012);
  _EQ012 = !STATE0 & !STATE1;

-- Node name is ':192' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ013);
  _EQ013 = !M1 &  STATE0
         # !M3 &  STATE0
         #  _LC4_A2;

-- Node name is ':193' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ014);
  _EQ014 =  _LC1_A2 &  M2 & !M3;

-- Node name is ':195' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ015);
  _EQ015 =  _LC6_A2 & !_LC7_A2
         #  _LC7_A2 & !M5
         #  _LC7_A2 & !M1;

-- Node name is ':400' 
-- Equation name is '_LC7_A5', type is buried 
_LC7_A5  = LCELL( _EQ016);
  _EQ016 =  STATE0 &  STATE1;



Project Information               d:\jiaotongdeng202040607\traffic_control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = off
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,541K