📄 cnt50.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\jiaotongdeng202040607\cnt50.rpt
cnt50
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\jiaotongdeng202040607\cnt50.rpt
cnt50
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
Device-Specific Information: d:\jiaotongdeng202040607\cnt50.rpt
cnt50
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 LOAD
Device-Specific Information: d:\jiaotongdeng202040607\cnt50.rpt
cnt50
** EQUATIONS **
CLK : INPUT;
EN : INPUT;
LOAD : INPUT;
-- Node name is ':22' = 'CNT0'
-- Equation name is 'CNT0', location is LC7_A19, type is buried.
CNT0 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ001 = !CNT0 & _LC2_A13;
-- Node name is ':21' = 'CNT1'
-- Equation name is 'CNT1', location is LC2_A19, type is buried.
!CNT1 = CNT1~NOT;
CNT1~NOT = DFFE( _EQ002, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ002 = !CNT0 & CNT1 & _LC2_A13
# CNT0 & !CNT1 & _LC2_A13;
-- Node name is ':20' = 'CNT2'
-- Equation name is 'CNT2', location is LC1_A19, type is buried.
CNT2 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ003 = CNT1 & CNT2 & _LC2_A13
# CNT0 & CNT2 & _LC2_A13
# !CNT0 & !CNT1 & !CNT2 & _LC2_A13;
-- Node name is ':19' = 'CNT3'
-- Equation name is 'CNT3', location is LC3_A19, type is buried.
CNT3 = DFFE( _EQ004, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ004 = CNT3 & _LC2_A13 & _LC6_A19
# !CNT3 & _LC2_A13 & !_LC6_A19;
-- Node name is ':18' = 'CNT4'
-- Equation name is 'CNT4', location is LC4_A19, type is buried.
!CNT4 = CNT4~NOT;
CNT4~NOT = DFFE( _EQ005, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ005 = CNT4 & _LC2_A13 & !_LC8_A19
# !CNT4 & _LC2_A13 & _LC8_A19;
-- Node name is ':17' = 'CNT5'
-- Equation name is 'CNT5', location is LC5_A19, type is buried.
!CNT5 = CNT5~NOT;
CNT5~NOT = DFFE( _EQ006, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ006 = !CNT4 & CNT5 & _LC2_A13 & !_LC8_A19
# CNT4 & !CNT5 & _LC2_A13
# !CNT5 & _LC2_A13 & _LC8_A19;
-- Node name is ':16' = 'CNT6'
-- Equation name is 'CNT6', location is LC8_A13, type is buried.
CNT6 = DFFE( _EQ007, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ007 = CNT6 & _LC2_A13 & _LC4_A13
# !CNT6 & _LC2_A13 & !_LC4_A13;
-- Node name is ':15' = 'CNT7'
-- Equation name is 'CNT7', location is LC1_A13, type is buried.
CNT7 = DFFE( _EQ008, GLOBAL( CLK), GLOBAL(!LOAD), VCC, VCC);
_EQ008 = CNT6 & CNT7 & _LC2_A13
# CNT7 & _LC2_A13 & _LC4_A13
# !CNT6 & !CNT7 & _LC2_A13 & !_LC4_A13;
-- Node name is 'Q50'
-- Equation name is 'Q50', type is output
Q50 = CNT0;
-- Node name is 'Q51'
-- Equation name is 'Q51', type is output
Q51 = CNT1;
-- Node name is 'Q52'
-- Equation name is 'Q52', type is output
Q52 = CNT2;
-- Node name is 'Q53'
-- Equation name is 'Q53', type is output
Q53 = CNT3;
-- Node name is 'Q54'
-- Equation name is 'Q54', type is output
Q54 = CNT4;
-- Node name is 'Q55'
-- Equation name is 'Q55', type is output
Q55 = CNT5;
-- Node name is 'Q56'
-- Equation name is 'Q56', type is output
Q56 = CNT6;
-- Node name is 'Q57'
-- Equation name is 'Q57', type is output
Q57 = CNT7;
-- Node name is 'S5'
-- Equation name is 'S5', type is output
S5 = !_LC3_A13;
-- Node name is '|LPM_ADD_SUB:86|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = LCELL( _EQ009);
_EQ009 = CNT1
# CNT0
# CNT2;
-- Node name is '|LPM_ADD_SUB:86|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = LCELL( _EQ010);
_EQ010 = CNT3
# CNT2
# CNT1
# CNT0;
-- Node name is '|LPM_ADD_SUB:86|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ011);
_EQ011 = CNT5
# CNT4
# _LC8_A19;
-- Node name is ':40'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = LCELL( _EQ012);
_EQ012 = CNT6
# _LC4_A13
# CNT7;
-- Node name is ':77'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ013);
_EQ013 = CNT7 & EN
# CNT6 & EN
# EN & _LC4_A13;
Project Information d:\jiaotongdeng202040607\cnt50.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,132K
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