📄 mux52.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX52 IS
PORT( A1,A2,A3,A4,A5:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MQ,BQ:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX52;
ARCHITECTURE ONE OF MUX52 IS
BEGIN
PROCESS(A1,A2,A3,A4,A5)
VARIABLE M,B:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF A4>0 THEN M:=A4 ;B:=A5;
ELSIF A5>0 THEN M:=A1 ;B:=A5;
ELSIF A2>0 THEN M:=A3; B:=A2;
ELSIF A3>0 THEN M:=A3; B:=A1;
END IF;
MQ<=M;BQ<=B;
END PROCESS;
END ARCHITECTURE ONE;
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