📄 jiaotong.rpt
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- 8 - B 37 OR2 0 3 1 1 |MUX52:6|:459
- 3 - B 09 OR2 s 0 4 0 1 |MUX52:6|~474~1
- 5 - B 37 OR2 0 3 1 1 |MUX52:6|:474
- 4 - B 09 OR2 s 0 4 0 1 |MUX52:6|~489~1
- 4 - B 36 OR2 0 3 1 1 |MUX52:6|:489
- 1 - B 08 OR2 s 0 4 0 1 |MUX52:6|~504~1
- 1 - B 33 OR2 0 3 1 1 |MUX52:6|:504
- 3 - B 08 OR2 s 0 4 0 1 |MUX52:6|~519~1
- 1 - B 30 OR2 0 3 1 1 |MUX52:6|:519
- 4 - B 08 OR2 s 0 4 0 1 |MUX52:6|~534~1
- 2 - B 28 OR2 0 3 1 1 |MUX52:6|:534
- 7 - B 25 OR2 s 0 4 0 1 |MUX52:6|~549~1
- 3 - B 25 OR2 0 3 1 1 |MUX52:6|:549
- 7 - B 23 OR2 s 0 4 0 1 |MUX52:6|~564~1
- 8 - B 23 OR2 s 0 3 0 1 |MUX52:6|~564~2
- 4 - B 23 OR2 0 4 1 1 |MUX52:6|:564
- 1 - B 24 OR2 s 0 4 0 1 |MUX52:6|~579~1
- 6 - B 24 OR2 0 4 1 1 |MUX52:6|:579
- 3 - B 22 OR2 s 0 4 0 1 |MUX52:6|~594~1
- 2 - B 22 OR2 0 4 1 1 |MUX52:6|:594
- 7 - B 21 OR2 s 0 4 0 1 |MUX52:6|~609~1
- 8 - B 21 OR2 0 4 1 1 |MUX52:6|:609
- 1 - B 22 OR2 s 0 4 0 1 |MUX52:6|~624~1
- 3 - B 21 OR2 0 4 1 1 |MUX52:6|:624
- 8 - B 19 OR2 s 0 4 0 1 |MUX52:6|~639~1
- 6 - B 19 OR2 0 4 1 1 |MUX52:6|:639
- 6 - B 20 OR2 s 0 4 0 1 |MUX52:6|~654~1
- 5 - B 20 OR2 0 4 1 1 |MUX52:6|:654
- 2 - B 18 OR2 s 0 4 0 1 |MUX52:6|~669~1
- 3 - B 17 AND2 s 0 3 0 7 |MUX52:6|~669~2
- 1 - B 18 OR2 0 4 1 1 |MUX52:6|:669
- 2 - B 47 DFFE +s 0 3 1 0 |TRAFFIC_CONTROL:26|STATE1~1 (|TRAFFIC_CONTROL:26|~18~1)
- 1 - B 47 DFFE + 0 3 1 11 |TRAFFIC_CONTROL:26|STATE1 (|TRAFFIC_CONTROL:26|:18)
- 8 - B 47 DFFE + 0 4 0 11 |TRAFFIC_CONTROL:26|STATE0 (|TRAFFIC_CONTROL:26|:19)
- 6 - B 47 OR2 ! 0 4 0 3 |TRAFFIC_CONTROL:26|:72
- 3 - B 47 OR2 ! 0 4 0 3 |TRAFFIC_CONTROL:26|:137
- 3 - B 15 AND2 0 2 1 3 |TRAFFIC_CONTROL:26|:167
- 1 - B 48 AND2 0 2 1 0 |TRAFFIC_CONTROL:26|:175
- 2 - B 50 AND2 0 2 1 3 |TRAFFIC_CONTROL:26|:183
- 5 - B 47 OR2 0 3 0 1 |TRAFFIC_CONTROL:26|:192
- 4 - B 47 AND2 0 3 0 1 |TRAFFIC_CONTROL:26|:193
- 7 - B 47 OR2 0 4 0 1 |TRAFFIC_CONTROL:26|:195
- 6 - B 15 AND2 0 2 1 0 |TRAFFIC_CONTROL:26|:400
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\jiaotongdeng202040607\jiaotong.rpt
jiaotong
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 46/208( 22%) 23/104( 22%) 4/104( 3%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 1/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
38: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
39: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
48: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\jiaotongdeng202040607\jiaotong.rpt
jiaotong
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 43 CLK
Device-Specific Information: d:\jiaotongdeng202040607\jiaotong.rpt
jiaotong
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 40 LOAD
Device-Specific Information: d:\jiaotongdeng202040607\jiaotong.rpt
jiaotong
** EQUATIONS **
CLK : INPUT;
LOAD : INPUT;
-- Node name is 'BG'
-- Equation name is 'BG', type is output
BG = _LC3_B15;
-- Node name is 'BQ0'
-- Equation name is 'BQ0', type is output
BQ0 = _LC1_B18;
-- Node name is 'BQ1'
-- Equation name is 'BQ1', type is output
BQ1 = _LC5_B20;
-- Node name is 'BQ2'
-- Equation name is 'BQ2', type is output
BQ2 = _LC6_B19;
-- Node name is 'BQ3'
-- Equation name is 'BQ3', type is output
BQ3 = _LC3_B21;
-- Node name is 'BQ4'
-- Equation name is 'BQ4', type is output
BQ4 = _LC8_B21;
-- Node name is 'BQ5'
-- Equation name is 'BQ5', type is output
BQ5 = _LC2_B22;
-- Node name is 'BQ6'
-- Equation name is 'BQ6', type is output
BQ6 = _LC6_B24;
-- Node name is 'BQ7'
-- Equation name is 'BQ7', type is output
BQ7 = _LC4_B23;
-- Node name is 'BR'
-- Equation name is 'BR', type is output
BR = !_LC1_B47;
-- Node name is 'BY'
-- Equation name is 'BY', type is output
BY = _LC6_B15;
-- Node name is 'MG'
-- Equation name is 'MG', type is output
MG = _LC2_B50;
-- Node name is 'MQ0'
-- Equation name is 'MQ0', type is output
MQ0 = _LC3_B25;
-- Node name is 'MQ1'
-- Equation name is 'MQ1', type is output
MQ1 = _LC2_B28;
-- Node name is 'MQ2'
-- Equation name is 'MQ2', type is output
MQ2 = _LC1_B30;
-- Node name is 'MQ3'
-- Equation name is 'MQ3', type is output
MQ3 = _LC1_B33;
-- Node name is 'MQ4'
-- Equation name is 'MQ4', type is output
MQ4 = _LC4_B36;
-- Node name is 'MQ5'
-- Equation name is 'MQ5', type is output
MQ5 = _LC5_B37;
-- Node name is 'MQ6'
-- Equation name is 'MQ6', type is output
MQ6 = _LC8_B37;
-- Node name is 'MQ7'
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