mux52.rpt

假设某个十字路口是由一条主干道和一条次干道汇合而成

         #  A15 &  _LC8_A21
         #  A15 &  A57;

-- Node name is ':474' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ019);
  _EQ019 = !A47 & !_LC1_C14 &  _LC8_C16
         #  A45;

-- Node name is '~489~1' 
-- Equation name is '~489~1', location is LC5_C16, type is buried.
-- synthesized logic cell 
_LC5_C16 = LCELL( _EQ020);
  _EQ020 = !_LC2_B13 & !_LC2_B24 &  _LC4_C16
         #  A34;

-- Node name is '~489~2' 
-- Equation name is '~489~2', location is LC6_C16, type is buried.
-- synthesized logic cell 
_LC6_C16 = LCELL( _EQ021);
  _EQ021 = !A57 &  _LC5_C16 & !_LC8_A21
         #  A14 &  _LC8_A21
         #  A14 &  A57;

-- Node name is ':489' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = LCELL( _EQ022);
  _EQ022 = !A47 & !_LC1_C14 &  _LC6_C16
         #  A44;

-- Node name is '~504~1' 
-- Equation name is '~504~1', location is LC7_B13, type is buried.
-- synthesized logic cell 
_LC7_B13 = LCELL( _EQ023);
  _EQ023 =  _LC1_B13 & !_LC2_B13 & !_LC2_B24
         #  A33;

-- Node name is '~504~2' 
-- Equation name is '~504~2', location is LC8_B13, type is buried.
-- synthesized logic cell 
_LC8_B13 = LCELL( _EQ024);
  _EQ024 = !A57 &  _LC7_B13 & !_LC8_A21
         #  A13 &  _LC8_A21
         #  A13 &  A57;

-- Node name is ':504' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = LCELL( _EQ025);
  _EQ025 = !A47 & !_LC1_C14 &  _LC8_B13
         #  A43;

-- Node name is '~519~1' 
-- Equation name is '~519~1', location is LC7_A21, type is buried.
-- synthesized logic cell 
_LC7_A21 = LCELL( _EQ026);
  _EQ026 = !_LC2_B13 & !_LC2_B24 &  _LC2_C14
         #  A32;

-- Node name is '~519~2' 
-- Equation name is '~519~2', location is LC6_A21, type is buried.
-- synthesized logic cell 
_LC6_A21 = LCELL( _EQ027);
  _EQ027 = !A57 &  _LC7_A21 & !_LC8_A21
         #  A12 &  _LC8_A21
         #  A12 &  A57;

-- Node name is ':519' 
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = LCELL( _EQ028);
  _EQ028 = !A47 & !_LC1_C14 &  _LC6_A21
         #  A42;

-- Node name is '~534~1' 
-- Equation name is '~534~1', location is LC7_C14, type is buried.
-- synthesized logic cell 
_LC7_C14 = LCELL( _EQ029);
  _EQ029 = !_LC2_B13 & !_LC2_B24 &  _LC5_C14
         #  A31;

-- Node name is '~534~2' 
-- Equation name is '~534~2', location is LC8_C14, type is buried.
-- synthesized logic cell 
_LC8_C14 = LCELL( _EQ030);
  _EQ030 = !A57 &  _LC7_C14 & !_LC8_A21
         #  A11 &  _LC8_A21
         #  A11 &  A57;

-- Node name is ':534' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = LCELL( _EQ031);
  _EQ031 = !A47 & !_LC1_C14 &  _LC8_C14
         #  A41;

-- Node name is '~549~1' 
-- Equation name is '~549~1', location is LC7_B20, type is buried.
-- synthesized logic cell 
_LC7_B20 = LCELL( _EQ032);
  _EQ032 = !_LC2_B13 & !_LC2_B24 &  _LC6_B20
         #  A30;

-- Node name is '~549~2' 
-- Equation name is '~549~2', location is LC8_B20, type is buried.
-- synthesized logic cell 
_LC8_B20 = LCELL( _EQ033);
  _EQ033 = !A57 &  _LC7_B20 & !_LC8_A21
         #  A10 &  _LC8_A21
         #  A10 &  A57;

-- Node name is ':549' 
-- Equation name is '_LC6_B20', type is buried 
_LC6_B20 = LCELL( _EQ034);
  _EQ034 = !A47 & !_LC1_C14 &  _LC8_B20
         #  A40;

-- Node name is '~564~1' 
-- Equation name is '~564~1', location is LC5_B13, type is buried.
-- synthesized logic cell 
_LC5_B13 = LCELL( _EQ035);
  _EQ035 = !_LC2_B24 &  _LC3_B13 & !_LC4_B13
         #  A17 &  _LC2_B24 & !_LC4_B13;

-- Node name is '~564~2' 
-- Equation name is '~564~2', location is LC6_B13, type is buried.
-- synthesized logic cell 
_LC6_B13 = LCELL( _EQ036);
  _EQ036 = !A47 & !_LC1_C14 & !_LC8_A21;

-- Node name is ':564' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = LCELL( _EQ037);
  _EQ037 =  _LC5_B13 &  _LC6_B13
         #  A27 &  _LC6_B13
         #  A57;

-- Node name is '~579~1' 
-- Equation name is '~579~1', location is LC2_A22, type is buried.
-- synthesized logic cell 
_LC2_A22 = LCELL( _EQ038);
  _EQ038 =  _LC1_A22 & !_LC2_B13 & !_LC2_B24
         #  A16 & !_LC2_B13 &  _LC2_B24;

-- Node name is ':579' 
-- Equation name is '_LC1_A22', type is buried 
_LC1_A22 = LCELL( _EQ039);
  _EQ039 =  _LC2_A22 &  _LC2_B20
         #  A26 &  _LC2_B20
         #  A56;

-- Node name is '~594~1' 
-- Equation name is '~594~1', location is LC1_B24, type is buried.
-- synthesized logic cell 
_LC1_B24 = LCELL( _EQ040);
  _EQ040 = !_LC2_B13 & !_LC2_B24 &  _LC8_B24
         #  A15 & !_LC2_B13 &  _LC2_B24;

-- Node name is ':594' 
-- Equation name is '_LC8_B24', type is buried 
_LC8_B24 = LCELL( _EQ041);
  _EQ041 =  _LC1_B24 &  _LC2_B20
         #  A25 &  _LC2_B20
         #  A55;

-- Node name is '~609~1' 
-- Equation name is '~609~1', location is LC3_C16, type is buried.
-- synthesized logic cell 
_LC3_C16 = LCELL( _EQ042);
  _EQ042 =  _LC1_C16 & !_LC2_B13 & !_LC2_B24
         #  A14 & !_LC2_B13 &  _LC2_B24;

-- Node name is ':609' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = LCELL( _EQ043);
  _EQ043 =  _LC2_B20 &  _LC3_C16
         #  A24 &  _LC2_B20
         #  A54;

-- Node name is '~624~1' 
-- Equation name is '~624~1', location is LC4_A21, type is buried.
-- synthesized logic cell 
_LC4_A21 = LCELL( _EQ044);
  _EQ044 = !_LC2_B13 & !_LC2_B24 &  _LC5_A21
         #  A13 & !_LC2_B13 &  _LC2_B24;

-- Node name is ':624' 
-- Equation name is '_LC5_A21', type is buried 
_LC5_A21 = LCELL( _EQ045);
  _EQ045 =  _LC2_B20 &  _LC4_A21
         #  A23 &  _LC2_B20
         #  A53;

-- Node name is '~639~1' 
-- Equation name is '~639~1', location is LC2_A21, type is buried.
-- synthesized logic cell 
_LC2_A21 = LCELL( _EQ046);
  _EQ046 = !_LC2_B13 & !_LC2_B24 &  _LC3_A21
         #  A12 & !_LC2_B13 &  _LC2_B24;

-- Node name is ':639' 
-- Equation name is '_LC3_A21', type is buried 
_LC3_A21 = LCELL( _EQ047);
  _EQ047 =  _LC2_A21 &  _LC2_B20
         #  A22 &  _LC2_B20
         #  A52;

-- Node name is '~654~1' 
-- Equation name is '~654~1', location is LC4_C14, type is buried.
-- synthesized logic cell 
_LC4_C14 = LCELL( _EQ048);
  _EQ048 = !_LC2_B13 & !_LC2_B24 &  _LC6_C14
         #  A11 & !_LC2_B13 &  _LC2_B24;

-- Node name is ':654' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = LCELL( _EQ049);
  _EQ049 =  _LC2_B20 &  _LC4_C14
         #  A21 &  _LC2_B20
         #  A51;

-- Node name is '~669~1' 
-- Equation name is '~669~1', location is LC5_B20, type is buried.
-- synthesized logic cell 
_LC5_B20 = LCELL( _EQ050);
  _EQ050 =  _LC1_B20 & !_LC2_B13 & !_LC2_B24
         #  A10 & !_LC2_B13 &  _LC2_B24;

-- Node name is '~669~2' 
-- Equation name is '~669~2', location is LC2_B20, type is buried.
-- synthesized logic cell 
_LC2_B20 = LCELL( _EQ051);
  _EQ051 = !A47 & !A57 & !_LC1_C14 & !_LC8_A21;

-- Node name is ':669' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ052);
  _EQ052 =  _LC2_B20 &  _LC5_B20
         #  A20 &  _LC2_B20
         #  A50;



Project Information                         d:\jiaotongdeng202040607\mux52.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,427K