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📄 mux52.rpt

📁 假设某个十字路口是由一条主干道和一条次干道汇合而成
💻 RPT
📖 第 1 页 / 共 3 页
字号:
   -      6     -    A    22        OR2    s           2    2    0    1  ~444~2
   -      7     -    A    22        OR2                1    2    1    1  :444
   -      3     -    A    22        OR2    s           1    3    0    1  ~459~1
   -      4     -    A    22        OR2    s           2    2    0    1  ~459~2
   -      8     -    A    22        OR2                2    2    1    1  :459
   -      7     -    C    16        OR2    s           1    3    0    1  ~474~1
   -      8     -    C    16        OR2    s           2    2    0    1  ~474~2
   -      2     -    C    16        OR2                2    2    1    1  :474
   -      5     -    C    16        OR2    s           1    3    0    1  ~489~1
   -      6     -    C    16        OR2    s           2    2    0    1  ~489~2
   -      4     -    C    16        OR2                2    2    1    1  :489
   -      7     -    B    13        OR2    s           1    3    0    1  ~504~1
   -      8     -    B    13        OR2    s           2    2    0    1  ~504~2
   -      1     -    B    13        OR2                2    2    1    1  :504
   -      7     -    A    21        OR2    s           1    3    0    1  ~519~1
   -      6     -    A    21        OR2    s           2    2    0    1  ~519~2
   -      2     -    C    14        OR2                2    2    1    1  :519
   -      7     -    C    14        OR2    s           1    3    0    1  ~534~1
   -      8     -    C    14        OR2    s           2    2    0    1  ~534~2
   -      5     -    C    14        OR2                2    2    1    1  :534
   -      7     -    B    20        OR2    s           1    3    0    1  ~549~1
   -      8     -    B    20        OR2    s           2    2    0    1  ~549~2
   -      6     -    B    20        OR2                2    2    1    1  :549
   -      5     -    B    13        OR2    s           1    3    0    1  ~564~1
   -      6     -    B    13       AND2    s           1    2    0    1  ~564~2
   -      3     -    B    13        OR2                2    2    1    1  :564
   -      2     -    A    22        OR2    s           1    3    0    1  ~579~1
   -      1     -    A    22        OR2                2    2    1    1  :579
   -      1     -    B    24        OR2    s           1    3    0    1  ~594~1
   -      8     -    B    24        OR2                2    2    1    1  :594
   -      3     -    C    16        OR2    s           1    3    0    1  ~609~1
   -      1     -    C    16        OR2                2    2    1    1  :609
   -      4     -    A    21        OR2    s           1    3    0    1  ~624~1
   -      5     -    A    21        OR2                2    2    1    1  :624
   -      2     -    A    21        OR2    s           1    3    0    1  ~639~1
   -      3     -    A    21        OR2                2    2    1    1  :639
   -      4     -    C    14        OR2    s           1    3    0    1  ~654~1
   -      6     -    C    14        OR2                2    2    1    1  :654
   -      5     -    B    20        OR2    s           1    3    0    1  ~669~1
   -      2     -    B    20       AND2    s           2    2    0    7  ~669~2
   -      1     -    B    20        OR2                2    2    1    1  :669


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register


Device-Specific Information:                d:\jiaotongdeng202040607\mux52.rpt
mux52

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      11/ 96( 11%)     0/ 48(  0%)    18/ 48( 37%)    5/16( 31%)      5/16( 31%)     0/16(  0%)
B:      13/ 96( 13%)     3/ 48(  6%)    16/ 48( 33%)    4/16( 25%)      5/16( 31%)     0/16(  0%)
C:      13/ 96( 13%)     0/ 48(  0%)    13/ 48( 27%)    4/16( 25%)      5/16( 31%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
03:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
19:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
20:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
24:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                d:\jiaotongdeng202040607\mux52.rpt
mux52

** EQUATIONS **

A10      : INPUT;
A11      : INPUT;
A12      : INPUT;
A13      : INPUT;
A14      : INPUT;
A15      : INPUT;
A16      : INPUT;
A17      : INPUT;
A20      : INPUT;
A21      : INPUT;
A22      : INPUT;
A23      : INPUT;
A24      : INPUT;
A25      : INPUT;
A26      : INPUT;
A27      : INPUT;
A30      : INPUT;
A31      : INPUT;
A32      : INPUT;
A33      : INPUT;
A34      : INPUT;
A35      : INPUT;
A36      : INPUT;
A37      : INPUT;
A40      : INPUT;
A41      : INPUT;
A42      : INPUT;
A43      : INPUT;
A44      : INPUT;
A45      : INPUT;
A46      : INPUT;
A47      : INPUT;
A50      : INPUT;
A51      : INPUT;
A52      : INPUT;
A53      : INPUT;
A54      : INPUT;
A55      : INPUT;
A56      : INPUT;
A57      : INPUT;

-- Node name is 'BQ0' 
-- Equation name is 'BQ0', type is output 
BQ0      =  _LC1_B20;

-- Node name is 'BQ1' 
-- Equation name is 'BQ1', type is output 
BQ1      =  _LC6_C14;

-- Node name is 'BQ2' 
-- Equation name is 'BQ2', type is output 
BQ2      =  _LC3_A21;

-- Node name is 'BQ3' 
-- Equation name is 'BQ3', type is output 
BQ3      =  _LC5_A21;

-- Node name is 'BQ4' 
-- Equation name is 'BQ4', type is output 
BQ4      =  _LC1_C16;

-- Node name is 'BQ5' 
-- Equation name is 'BQ5', type is output 
BQ5      =  _LC8_B24;

-- Node name is 'BQ6' 
-- Equation name is 'BQ6', type is output 
BQ6      =  _LC1_A22;

-- Node name is 'BQ7' 
-- Equation name is 'BQ7', type is output 
BQ7      =  _LC3_B13;

-- Node name is 'MQ0' 
-- Equation name is 'MQ0', type is output 
MQ0      =  _LC6_B20;

-- Node name is 'MQ1' 
-- Equation name is 'MQ1', type is output 
MQ1      =  _LC5_C14;

-- Node name is 'MQ2' 
-- Equation name is 'MQ2', type is output 
MQ2      =  _LC2_C14;

-- Node name is 'MQ3' 
-- Equation name is 'MQ3', type is output 
MQ3      =  _LC1_B13;

-- Node name is 'MQ4' 
-- Equation name is 'MQ4', type is output 
MQ4      =  _LC4_C16;

-- Node name is 'MQ5' 
-- Equation name is 'MQ5', type is output 
MQ5      =  _LC2_C16;

-- Node name is 'MQ6' 
-- Equation name is 'MQ6', type is output 
MQ6      =  _LC8_A22;

-- Node name is 'MQ7' 
-- Equation name is 'MQ7', type is output 
MQ7      =  _LC7_A22;

-- Node name is '~122~1' 
-- Equation name is '~122~1', location is LC3_C14, type is buried.
-- synthesized logic cell 
_LC3_C14 = LCELL( _EQ001);
  _EQ001 = !A40 & !A41 & !A42 & !A43;

-- Node name is ':122' 
-- Equation name is '_LC1_C14', type is buried 
!_LC1_C14 = _LC1_C14~NOT;
_LC1_C14~NOT = LCELL( _EQ002);
  _EQ002 = !A44 & !A45 & !A46 &  _LC3_C14;

-- Node name is '~167~1' 
-- Equation name is '~167~1', location is LC1_A21, type is buried.
-- synthesized logic cell 
_LC1_A21 = LCELL( _EQ003);
  _EQ003 = !A50 & !A51 & !A52 & !A53;

-- Node name is ':167' 
-- Equation name is '_LC8_A21', type is buried 
!_LC8_A21 = _LC8_A21~NOT;
_LC8_A21~NOT = LCELL( _EQ004);
  _EQ004 = !A54 & !A55 & !A56 &  _LC1_A21;

-- Node name is ':207' 
-- Equation name is '_LC2_B13', type is buried 
!_LC2_B13 = _LC2_B13~NOT;
_LC2_B13~NOT = LCELL( _EQ005);
  _EQ005 = !A27 & !_LC4_B13;

-- Node name is '~212~1' 
-- Equation name is '~212~1', location is LC2_B6, type is buried.
-- synthesized logic cell 
_LC2_B6  = LCELL( _EQ006);
  _EQ006 = !A20 & !A21 & !A22 & !A23;

-- Node name is ':212' 
-- Equation name is '_LC4_B13', type is buried 
!_LC4_B13 = _LC4_B13~NOT;
_LC4_B13~NOT = LCELL( _EQ007);
  _EQ007 = !A24 & !A25 & !A26 &  _LC2_B6;

-- Node name is ':252' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = LCELL( _EQ008);
  _EQ008 =  _LC3_B20
         #  A37;

-- Node name is '~257~1' 
-- Equation name is '~257~1', location is LC4_B20, type is buried.
-- synthesized logic cell 
!_LC4_B20 = _LC4_B20~NOT;
_LC4_B20~NOT = LCELL( _EQ009);
  _EQ009 =  A33
         #  A32
         #  A31
         #  A30;

-- Node name is ':257' 
-- Equation name is '_LC3_B20', type is buried 
_LC3_B20 = LCELL( _EQ010);
  _EQ010 =  A36
         #  A35
         #  A34
         # !_LC4_B20;

-- Node name is '~444~1' 
-- Equation name is '~444~1', location is LC5_A22, type is buried.
-- synthesized logic cell 
_LC5_A22 = LCELL( _EQ011);
  _EQ011 = !_LC2_B13 & !_LC3_B20 &  _LC7_A22
         #  A37;

-- Node name is '~444~2' 
-- Equation name is '~444~2', location is LC6_A22, type is buried.
-- synthesized logic cell 
_LC6_A22 = LCELL( _EQ012);
  _EQ012 = !A57 &  _LC5_A22 & !_LC8_A21
         #  A17 &  _LC8_A21
         #  A17 &  A57;

-- Node name is ':444' 
-- Equation name is '_LC7_A22', type is buried 
_LC7_A22 = LCELL( _EQ013);
  _EQ013 = !_LC1_C14 &  _LC6_A22
         #  A47;

-- Node name is '~459~1' 
-- Equation name is '~459~1', location is LC3_A22, type is buried.
-- synthesized logic cell 
_LC3_A22 = LCELL( _EQ014);
  _EQ014 = !_LC2_B13 & !_LC2_B24 &  _LC8_A22
         #  A36;

-- Node name is '~459~2' 
-- Equation name is '~459~2', location is LC4_A22, type is buried.
-- synthesized logic cell 
_LC4_A22 = LCELL( _EQ015);
  _EQ015 = !A57 &  _LC3_A22 & !_LC8_A21
         #  A16 &  _LC8_A21
         #  A16 &  A57;

-- Node name is ':459' 
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ016);
  _EQ016 = !A47 & !_LC1_C14 &  _LC4_A22
         #  A46;

-- Node name is '~474~1' 
-- Equation name is '~474~1', location is LC7_C16, type is buried.
-- synthesized logic cell 
_LC7_C16 = LCELL( _EQ017);
  _EQ017 = !_LC2_B13 & !_LC2_B24 &  _LC2_C16
         #  A35;

-- Node name is '~474~2' 
-- Equation name is '~474~2', location is LC8_C16, type is buried.
-- synthesized logic cell 
_LC8_C16 = LCELL( _EQ018);
  _EQ018 = !A57 &  _LC7_C16 & !_LC8_A21

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