📄 mux52.rpt
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Project Information d:\jiaotongdeng202040607\mux52.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/16/2007 08:01:18
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MUX52
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
mux52 EP1K10TC100-1 40 16 0 0 0 % 52 9 %
User Pins: 40 16 0
Project Information d:\jiaotongdeng202040607\mux52.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K10TC100-1 are preliminary
Device-Specific Information: d:\jiaotongdeng202040607\mux52.rpt
mux52
***** Logic for device 'mux52' compiled without errors.
Device: EP1K10TC100-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
Device-Specific Information: d:\jiaotongdeng202040607\mux52.rpt
mux52
** ERROR SUMMARY **
Info: Chip 'mux52' in device 'EP1K10TC100-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R R R R
E E E E E E
V S S S S S S ^
C E E V E E E E D
# C R R C R R R R A
T A A A A G A A I A A A G V A A V C A A V V V V T
C 4 3 4 5 N 3 2 N 3 3 3 N E 4 5 E I 2 2 E E E E A
K 0 7 6 5 D 1 6 T 5 3 6 D D 2 4 D O 0 1 D D D D 0
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
^CONF_DONE | 1 75 | ^DCLK
^nCEO | 2 74 | ^nCE
#TDO | 3 73 | #TDI
VCCIO | 4 72 | VCCINT
A16 | 5 71 | A52
BQ6 | 6 70 | A12
BQ2 | 7 69 | A56
BQ3 | 8 68 | A53
MQ7 | 9 67 | VCCIO
MQ6 | 10 66 | GND
GND | 11 65 | MQ3
VCCINT | 12 64 | A27
BQ0 | 13 EP1K10TC100-1 63 | A25
BQ7 | 14 62 | A30
BQ5 | 15 61 | A10
MQ0 | 16 60 | VCCINT
VCCIO | 17 59 | GND
GND | 18 58 | A14
BQ4 | 19 57 | A41
MQ5 | 20 56 | A44
MQ4 | 21 55 | A11
MQ1 | 22 54 | ^MSEL0
BQ1 | 23 53 | ^MSEL1
#TMS | 24 52 | VCCINT
^nSTATUS | 25 51 | ^nCONFIG
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
A A A A A A A A M V G V A A A G G R V R R R A A A
5 1 3 1 1 5 4 2 Q C N C 5 3 4 N N E C E E E 2 4 2
0 5 2 7 3 1 3 4 2 C D C 7 4 7 D D S C S S S 2 5 3
I _ _ E I E E E
N C C R O R R R
T K K V V V V
L L E E E E
K K D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\jiaotongdeng202040607\mux52.rpt
mux52
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A21 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
A22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
B6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
B20 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 17/22( 77%)
B24 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C14 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 18/22( 81%)
C16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 50/60 ( 83%)
Total logic cells used: 52/576 ( 9%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.88/4 ( 97%)
Total fan-in: 202/2304 ( 8%)
Total input pins required: 40
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 52
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 30/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 16/0
B: 0 0 0 0 0 1 0 0 0 0 0 0 0 8 0 0 0 0 0 0 8 0 0 0 3 20/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 0 0 0 0 0 0 0 16/0
Total: 0 0 0 0 0 1 0 0 0 0 0 0 0 8 8 0 8 0 0 0 8 8 8 0 3 52/0
Device-Specific Information: d:\jiaotongdeng202040607\mux52.rpt
mux52
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
61 - - B -- INPUT ^ 0 0 0 2 A10
55 - - C -- INPUT ^ 0 0 0 2 A11
70 - - A -- INPUT ^ 0 0 0 2 A12
30 - - - 18 INPUT ^ 0 0 0 2 A13
58 - - C -- INPUT ^ 0 0 0 2 A14
27 - - - 21 INPUT ^ 0 0 0 2 A15
5 - - A -- INPUT ^ 0 0 0 2 A16
29 - - - 19 INPUT ^ 0 0 0 2 A17
82 - - - 04 INPUT ^ 0 0 0 2 A20
81 - - - 03 INPUT ^ 0 0 0 2 A21
48 - - - 07 INPUT ^ 0 0 0 2 A22
50 - - - 02 INPUT ^ 0 0 0 2 A23
33 - - - 15 INPUT ^ 0 0 0 2 A24
63 - - B -- INPUT ^ 0 0 0 2 A25
93 - - - 13 INPUT ^ 0 0 0 2 A26
64 - - B -- INPUT ^ 0 0 0 2 A27
62 - - B -- INPUT ^ 0 0 0 2 A30
94 - - - 19 INPUT ^ 0 0 0 2 A31
28 - - - 20 INPUT ^ 0 0 0 2 A32
90 - - - -- INPUT ^ 0 0 0 2 A33
39 - - - -- INPUT ^ 0 0 0 2 A34
91 - - - -- INPUT ^ 0 0 0 2 A35
89 - - - -- INPUT ^ 0 0 0 2 A36
98 - - - 24 INPUT ^ 0 0 0 2 A37
99 - - - 24 INPUT ^ 0 0 0 2 A40
57 - - C -- INPUT ^ 0 0 0 2 A41
86 - - - 09 INPUT ^ 0 0 0 2 A42
32 - - - 16 INPUT ^ 0 0 0 2 A43
56 - - C -- INPUT ^ 0 0 0 2 A44
49 - - - 06 INPUT ^ 0 0 0 2 A45
97 - - - 23 INPUT ^ 0 0 0 2 A46
40 - - - -- INPUT ^ 0 0 0 10 A47
26 - - - 23 INPUT ^ 0 0 0 2 A50
31 - - - 17 INPUT ^ 0 0 0 2 A51
71 - - A -- INPUT ^ 0 0 0 2 A52
68 - - A -- INPUT ^ 0 0 0 2 A53
85 - - - 08 INPUT ^ 0 0 0 2 A54
96 - - - 22 INPUT ^ 0 0 0 2 A55
69 - - A -- INPUT ^ 0 0 0 2 A56
38 - - - -- INPUT ^ 0 0 0 10 A57
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\jiaotongdeng202040607\mux52.rpt
mux52
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
13 - - B -- OUTPUT 0 1 0 0 BQ0
23 - - C -- OUTPUT 0 1 0 0 BQ1
7 - - A -- OUTPUT 0 1 0 0 BQ2
8 - - A -- OUTPUT 0 1 0 0 BQ3
19 - - C -- OUTPUT 0 1 0 0 BQ4
15 - - B -- OUTPUT 0 1 0 0 BQ5
6 - - A -- OUTPUT 0 1 0 0 BQ6
14 - - B -- OUTPUT 0 1 0 0 BQ7
16 - - B -- OUTPUT 0 1 0 0 MQ0
22 - - C -- OUTPUT 0 1 0 0 MQ1
34 - - - 14 OUTPUT 0 1 0 0 MQ2
65 - - B -- OUTPUT 0 1 0 0 MQ3
21 - - C -- OUTPUT 0 1 0 0 MQ4
20 - - C -- OUTPUT 0 1 0 0 MQ5
10 - - A -- OUTPUT 0 1 0 0 MQ6
9 - - A -- OUTPUT 0 1 0 0 MQ7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\jiaotongdeng202040607\mux52.rpt
mux52
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 14 AND2 s 4 0 0 1 ~122~1
- 1 - C 14 AND2 ! 3 1 0 10 :122
- 1 - A 21 AND2 s 4 0 0 1 ~167~1
- 8 - A 21 AND2 ! 3 1 0 10 :167
- 2 - B 13 AND2 ! 1 1 0 15 :207
- 2 - B 06 AND2 s 4 0 0 1 ~212~1
- 4 - B 13 AND2 ! 3 1 0 2 :212
- 2 - B 24 OR2 1 1 0 15 :252
- 4 - B 20 OR2 s ! 4 0 0 1 ~257~1
- 3 - B 20 OR2 3 1 0 2 :257
- 5 - A 22 OR2 s 1 3 0 1 ~444~1
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