delay_rst_1.txt

来自「SAA7114 和 FPGA/CPLD之间通讯的程序」· 文本 代码 · 共 34 行

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DELAY_RST IS
   PORT (       RST              :IN  STD_LOGIC; -- 来自于SAA711
                CLK              :IN  STD_LOGIC;
                RST_OUT          :OUT STD_LOGIC  -- 输出到CPLD                        
         );
                
 END DELAY_RST;

ARCHITECTURE RTL OF DELAY_RST IS
SIGNAL  COUNTER: STD_LOGIC_VECTOR(15 DOWNTO 0):="0000000000000000";

BEGIN
 PROCESS(CLK)
 
 BEGIN
  IF rising_edge(Clk) THEN 
    IF (RST='0') THEN
       COUNTER<="1111100000000000";      --63488
	     RST_OUT<='0';
    ELSE     
	   IF(COUNTER="0000000000000000")THEN	      
		  RST_OUT<='1';
	   ELSE
          COUNTER<=COUNTER-'1';
	       RST_OUT<='0';
       END IF;
     END IF;   
   END IF;    
 END PROCESS;   
END RTL;