ram.fit

用VHDL编的简易CPU

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 03/19/2008 20:45:31      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "ram"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "address0"                     : INPUT_PIN  = 7      ;
    "address1"                     : INPUT_PIN  = 5      ;
    "address2"                     : INPUT_PIN  = 35     ;
    "address3"                     : INPUT_PIN  = 38     ;
    "address4"                     : INPUT_PIN  = 43     ;
    "address5"                     : INPUT_PIN  = 84     ;
    "address6"                     : INPUT_PIN  = 44     ;
    "address7"                     : INPUT_PIN  = 42     ;
    "clk"                          : INPUT_PIN  = 1      ;
    "c11"                          : INPUT_PIN  = 2      ;
    "data0"                        : INPUT_PIN  = 62     ;
    "data1"                        : INPUT_PIN  = 67     ;
    "data2"                        : INPUT_PIN  = 37     ;
    "data3"                        : INPUT_PIN  = 6      ;
    "data4"                        : INPUT_PIN  = 25     ;
    "data5"                        : INPUT_PIN  = 39     ;
    "data6"                        : INPUT_PIN  = 66     ;
    "data7"                        : INPUT_PIN  = 21     ;
    "data8"                        : INPUT_PIN  = 11     ;
    "data9"                        : INPUT_PIN  = 8      ;
    "data10"                       : INPUT_PIN  = 27     ;
    "data11"                       : INPUT_PIN  = 9      ;
    "data12"                       : INPUT_PIN  = 59     ;
    "data13"                       : INPUT_PIN  = 36     ;
    "data14"                       : INPUT_PIN  = 28     ;
    "data15"                       : INPUT_PIN  = 30     ;
    "MBR0"                         : OUTPUT_PIN = 60     ;
    "MBR1"                         : OUTPUT_PIN = 64     ;
    "MBR2"                         : OUTPUT_PIN = 69     ;
    "MBR3"                         : OUTPUT_PIN = 49     ;
    "MBR4"                         : OUTPUT_PIN = 65     ;
    "MBR5"                         : OUTPUT_PIN = 17     ;
    "MBR6"                         : OUTPUT_PIN = 50     ;
    "MBR7"                         : OUTPUT_PIN = 24     ;
    "MBR8"                         : OUTPUT_PIN = 80     ;
    "MBR9"                         : OUTPUT_PIN = 61     ;
    "MBR10"                        : OUTPUT_PIN = 18     ;
    "MBR11"                        : OUTPUT_PIN = 22     ;
    "MBR12"                        : OUTPUT_PIN = 29     ;
    "MBR13"                        : OUTPUT_PIN = 58     ;
    "MBR14"                        : OUTPUT_PIN = 71     ;
    "MBR15"                        : OUTPUT_PIN = 23     ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_0" : LOCATION   = EC2_C  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_1" : LOCATION   = EC4_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_2" : LOCATION   = EC2_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_3" : LOCATION   = EC1_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_4" : LOCATION   = EC3_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_5" : LOCATION   = EC5_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_6" : LOCATION   = EC6_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_7" : LOCATION   = EC7_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_8" : LOCATION   = EC8_B  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_9" : LOCATION   = EC1_C  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_10" : LOCATION   = EC5_C  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_11" : LOCATION   = EC3_C  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_12" : LOCATION   = EC4_C  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_13" : LOCATION   = EC7_C  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_14" : LOCATION   = EC6_C  ;
    "|LPM_RAM_DQ:1|altram:sram|segment0_15" : LOCATION   = EC8_C  ;

END;

INTERNAL_INFO "ram"
BEGIN
	DEVICE = EPF10K10LC84-3;
    OV0C2P7 : LORAX = "1:V1C2|2:HHL21R1,RP15R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:HHL21R2,RP14R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OV1C4P5 : LORAX = "1:V8C4|2:HHL0R1,RP1R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:HHL0R2,RP1R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OV2C5P35 : LORAX = "1:V14C5|2:HHL30R1,RP5R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:HHL30R2,RP13R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OV3C9P38 : LORAX = "1:V18C9|2:HHL26R1,RP21R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:HHL26R2,RP9R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OD5P43  : LORAX = "1:FB5|2:CH1R1,RP7R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:CH1R2,RP7R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OD0P84  : LORAX = "1:FB0|2:FH0R1,RP12R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:FH0R2,RP12R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OD2P44  : LORAX = "1:FB2|2:FH2R1,RP6R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:FH2R2,RP21R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OD3P42  : LORAX = "1:FB3|2:FH3R1,RP18R1->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B|,2:FH3R2,RP5R2->EC2_C,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C||";
    OD4P1   : LORAX = "1:FB4->EC2_C,->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C|";
    OD1P2   : LORAX = "1:FB1->EC2_C,->EC4_B,->EC2_B,->EC1_B,->EC3_B,->EC5_B,->EC6_B,->EC7_B,->EC8_B,->EC1_C,->EC5_C,->EC3_C,->EC4_C,->EC7_C,->EC6_C,->EC8_C|";
    OH0R2P62 : LORAX = "1:G10R2,RP11R2->EC2_C|";
    OH0R1P67 : LORAX = "1:G10R1,RP11R1->EC4_B|";
    OV3C8P37 : LORAX = "1:V18C8,HHL40R1,RP9R1->EC2_B|";
    OV0C3P6 : LORAX = "1:V1C3,HHL19R1,RP17R1->EC1_B|";
    OH15R1P25 : LORAX = "1:G39R1,RP20R1->EC3_B|";
    OV3C10P39 : LORAX = "1:V18C10,HHL31R1,RP14R1->EC5_B|";
    OH2R1P66 : LORAX = "1:G46R1,RP4R1->EC6_B|";
    OH8R1P21 : LORAX = "1:G13R1,RP0R1->EC7_B|";
    OV1C0P11 : LORAX = "1:V8C0,HHL3R1,RP19R1->EC8_B|";
    OV1C2P8 : LORAX = "1:V8C2,HHL1R2,RP0R2->EC1_C|";
    OH8R2P27 : LORAX = "1:G13R2,RP4R2->EC5_C|";
    OV1C1P9 : LORAX = "1:V8C1,HHL4R2,RP15R2->EC3_C|";
    OH4R2P59 : LORAX = "1:G47R2,RP3R2->EC4_C|";
    OV2C6P36 : LORAX = "1:V14C6,HHL41R2,RP8R2->EC7_C|";
    OH10R2P28 : LORAX = "1:G41R2,RP18R2->EC6_C|";
    OH14R2P30 : LORAX = "1:G44R2,RP6R2->EC8_C|";
    EC2_C   : LORAX = "1:RB1R2,G21R2->OH3R2P60|";
    EC4_B   : LORAX = "1:RB3R1,G92R1->OH6R1P64|";
    EC2_B   : LORAX = "1:RB1R1,RV17,G65R0->OH7R0P69|";
    EC1_B   : LORAX = "1:RB0R1,G75R1,V23C15->OV3C15P49|";
    EC3_B   : LORAX = "1:RB2R1,G85R1->OH4R1P65|";
    EC5_B   : LORAX = "1:RB4R1,RV8,G3R0->OH10R0P17|";
    EC6_B   : LORAX = "1:RB5R1,G22R1,V5C16->OV3C16P50|";
    EC7_B   : LORAX = "1:RB6R1,G84R1,V17C8,HHL45R1->OH13R1P24|";
    EC8_B   : LORAX = "1:RB7R1,G31R1,V5C22->OV0C22P80|";
    EC1_C   : LORAX = "1:RB0R2,G3R2->OH2R2P61|";
    EC5_C   : LORAX = "1:RB4R2,RV10,G85R0->OH12R0P18|";
    EC3_C   : LORAX = "1:RB2R2,G22R2,V4C4,HHL5R1->OH9R1P22|";
    EC4_C   : LORAX = "1:RB3R2,G60R2->OH12R2P29|";
    EC7_C   : LORAX = "1:RB6R2,G92R2->OH6R2P58|";
    EC6_C   : LORAX = "1:RB5R2,G35R2,V10C15,HHR17R0->OH3R0P71|";
    EC8_C   : LORAX = "1:RB7R2,G34R2,V10C21,G33R1->OH11R1P23|";
END;