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📄 cpu.hif

📁 用VHDL编的简易CPU
💻 HIF
字号:
HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	acc_alu.vhd
	{
		acc_alu [] [U3877600.DLS,U4470260.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			31 [] [];
		}
	}
	pc_reg.vhd
	{
		pc_reg [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			29 [] [];
		}
	}
	mar_reg.vhd
	{
		mar_reg [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			23 [] [];
		}
	}
	ir_opcode.vhd
	{
		ir_opcode [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			19 [] [];
		}
	}
	b_reg.vhd
	{
		b_reg [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			16 [] [];
		}
	}
	mbr_reg.vhd
	{
		mbr_reg [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			30 [] [];
		}
	}
	rom.gdf
	{
		rom [] []
		{
			20 [] [];
		}
	}
	lpm_ram_dq.tdf
	{
		lpm_ram_dq [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_WIDTHAD,LPM_NUMWORDS,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=REGISTERED,LPM_FILE=NO_FILE,DEVICE_FAMILY] [aglobal.inc,lpm_decode.inc,lpm_mux.inc,altram.inc]
		{
			24 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_INDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=UNREGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="d:\cpu\ram.mif",DEVICE_FAMILY=FLEX10K] [data15,data14,data13,data12,data11,data10,data9,data8,data7,data6,data5,data4,data3,data2,data1,data0,address7,address6,address5,address4,address3,address2,address1,address0,we,q15,q14,q13,q12,q11,q10,q9,q8,q7,q6,q5,q4,q3,q2,q1,q0];
		}
	}
	mr_reg.vhd
	{
		mr_reg [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U4470260.DLS,U3877600.DLS]
		{
			18 [] [];
		}
	}
	mpychoose_reg.vhd
	{
		mpychoose_reg [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U9092257.DLS,U5125632.DLS]
		{
			17 [] [];
		}
	}
	counter_reg.vhd
	{
		counter_reg [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U9092257.DLS,U5125632.DLS]
		{
			11 [] [];
		}
	}
	car.vhd
	{
		car [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			7 [] [];
		}
	}
	bl.vhd
	{
		bl [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			26 [] [];
		}
	}
	lpm_rom.tdf
	{
		lpm_rom [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_WIDTHAD,LPM_NUMWORDS,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=REGISTERED,LPM_FILE,DEVICE_FAMILY] [aglobal.inc,altrom.inc]
		{
			21 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=32,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_ADDRESS_CONTROL=UNREGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE=rom.mif,DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,q31,q30,q29,q28,q27,q26,q25,q24,q23,q22,q21,q20,q19,q18,q17,q16,q15,q14,q13,q12,q11,q10,q9,q8,q7,q6,q5,q4,q3,q2,q1,q0];
			27 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=32,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_ADDRESS_CONTROL=UNREGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="d:\cpu\rom.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,q31,q30,q29,q28,q27,q26,q25,q24,q23,q22,q21,q20,q19,q18,q17,q16,q15,q14,q13,q12,q11,q10,q9,q8,q7,q6,q5,q4,q3,q2,q1,q0];
		}
	}
	lpm_add_sub.tdf
	{
		lpm_add_sub [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=NO,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY,STYLE] [aglobal.inc,altshift.inc,bypassff.inc,look_add.inc,addcore.inc,lpm_add_sub.inc]
		{
			2 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=16,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=NO,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA0,DATAA1,DATAA2,DATAA3,DATAA4,DATAA5,DATAA6,DATAA7,DATAA8,DATAA9,DATAA10,DATAA11,DATAA12,DATAA13,DATAA14,DATAA15,DATAB0,DATAB1,DATAB2,DATAB3,DATAB4,DATAB5,DATAB6,DATAB7,DATAB8,DATAB9,DATAB10,DATAB11,DATAB12,DATAB13,DATAB14,DATAB15,CIN,RESULT0,RESULT1,RESULT2,RESULT3,RESULT4,RESULT5,RESULT6,RESULT7,RESULT8,RESULT9,RESULT10,RESULT11,RESULT12,RESULT13,RESULT14,RESULT15];
			8 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=YES,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA0,DATAA1,DATAA2,DATAA3,DATAA4,DATAA5,DATAA6,DATAA7,DATAB0,DATAB1,DATAB2,DATAB3,DATAB4,DATAB5,DATAB6,DATAB7,cin,RESULT0,RESULT1,RESULT2,RESULT3,RESULT4,RESULT5,RESULT6,RESULT7];
			12 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=5,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=YES,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA0,DATAA1,DATAA2,DATAA3,DATAA4,DATAB0,DATAB1,DATAB2,DATAB3,DATAB4,CIN,RESULT0,RESULT1,RESULT2,RESULT3,RESULT4];
			1 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=4,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=YES,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA0,DATAA1,DATAA2,DATAA3,DATAB0,DATAB1,DATAB2,DATAB3,CIN,RESULT0,RESULT1,RESULT2,RESULT3];
		}
	}
	addcore.tdf
	{
		addcore [USE_LPM_FOR_AHDL_OPERATORS,width,CONSTANT_CIN,CARRY_CHAIN,CARRY_CHAIN_LENGTH,DEVICE_FAMILY] [aglobal.inc,addcore.inc]
		{
			3 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=16,CONSTANT_CIN=0,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,datab2,datab3,datab4,datab5,datab6,datab7,datab8,datab9,datab10,datab11,datab12,datab13,datab14,datab15,dataa0,dataa1,dataa2,dataa3,dataa4,dataa5,dataa6,dataa7,dataa8,dataa9,dataa10,dataa11,dataa12,dataa13,dataa14,dataa15,result0,result1,result2,result3,result4,result5,result6,result7,result8,result9,result10,result11,result12,result13,result14,result15];
			9 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=8,CONSTANT_CIN=0,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,datab2,datab3,datab4,datab5,datab6,datab7,dataa0,dataa1,dataa2,dataa3,dataa4,dataa5,dataa6,dataa7,result0,result1,result2,result3,result4,result5,result6,result7];
			13 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=5,CONSTANT_CIN=0,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,datab2,datab3,datab4,dataa0,dataa1,dataa2,dataa3,dataa4,result0,result1,result2,result3,result4];
			6 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=4,CONSTANT_CIN=0,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,datab2,datab3,dataa0,dataa1,dataa2,dataa3,result0,result1,result2,result3];
		}
	}
	altshift.tdf
	{
		altshift [USE_LPM_FOR_AHDL_OPERATORS,WIDTH=4,DEPTH=0] []
		{
			4 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=16,DEPTH=0] [data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,data10,data11,data12,data13,data14,data15,result0,result1,result2,result3,result4,result5,result6,result7,result8,result9,result10,result11,result12,result13,result14,result15];
			5 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=1,DEPTH=0] [data0,result0];
			10 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,DEPTH=0] [data0,data1,data2,data3,data4,data5,data6,data7,result0,result1,result2,result3,result4,result5,result6,result7];
			14 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=5,DEPTH=0] [data0,data1,data2,data3,data4,result0,result1,result2,result3,result4];
			15 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=4,DEPTH=0] [data0,data1,data2,data3,result0,result1,result2,result3];
		}
	}
	altrom.tdf
	{
		altrom [USE_LPM_FOR_AHDL_OPERATORS,WIDTH,AD_WIDTH,NUMWORDS,FILE,REGISTERINPUTMODE=DEFAULT,DEVICE_FAMILY] [aglobal.inc,lpm_mux.inc,lpm_decode.inc,memmodes.inc]
		{
			22 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=32,AD_WIDTH=8,NUMWORDS=256,FILE=rom.mif,REGISTERINPUTMODE=DEFAULT,DEVICE_FAMILY=FLEX10K] [Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18,Q19,Q20,Q21,Q22,Q23,Q24,Q25,Q26,Q27,Q28,Q29,Q30,Q31];
			28 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=32,AD_WIDTH=8,NUMWORDS=256,FILE="d:\cpu\rom.mif",REGISTERINPUTMODE=DEFAULT,DEVICE_FAMILY=FLEX10K] [Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18,Q19,Q20,Q21,Q22,Q23,Q24,Q25,Q26,Q27,Q28,Q29,Q30,Q31];
		}
	}
	altram.tdf
	{
		altram [USE_LPM_FOR_AHDL_OPERATORS,WIDTH,AD_WIDTH,NUMWORDS,FILE=NO_FILE,REGISTERINPUTMODE=DEFAULT,USE_EAB=ON,DEVICE_FAMILY] [aglobal.inc,lpm_mux.inc,lpm_decode.inc,memmodes.inc]
		{
			25 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=16,AD_WIDTH=8,NUMWORDS=256,FILE="d:\cpu\ram.mif",REGISTERINPUTMODE=DEFAULT,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,Data8,Data9,Data10,Data11,Data12,Data13,Data14,Data15,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15];
		}
	}
	cpu.gdf
	{
		cpu [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	cpu::(0,0):(0): cpu.gdf
	{
		bl::(0,0):(51): bl.vhd;
		acc_alu::(0,0):(49): acc_alu.vhd
		{
			lpm_add_sub:2:(29,21):(372): lpm_add_sub.tdf
			{
				addcore:3:(212,4):(82,adder): addcore.tdf;
				altshift:4:(222,2):(137,result_ext_latency_ffs): altshift.tdf;
				altshift:5:(224,2):(175,carry_ext_latency_ffs): altshift.tdf;
				altshift:5:(226,2):(183,oflow_ext_latency_ffs): altshift.tdf;
			}
			lpm_add_sub:2:(31,21):(485): lpm_add_sub.tdf
			{
				addcore:3:(212,4):(82,adder): addcore.tdf;
				altshift:4:(222,2):(137,result_ext_latency_ffs): altshift.tdf;
				altshift:5:(224,2):(175,carry_ext_latency_ffs): altshift.tdf;
				altshift:5:(226,2):(183,oflow_ext_latency_ffs): altshift.tdf;
			}
		}
		car::(0,0):(31): car.vhd
		{
			lpm_add_sub:8:(20,25):(102): lpm_add_sub.tdf
			{
				addcore:9:(212,4):(58,adder): addcore.tdf;
				altshift:10:(222,2):(89,result_ext_latency_ffs): altshift.tdf;
				altshift:5:(224,2):(111,carry_ext_latency_ffs): altshift.tdf;
				altshift:5:(226,2):(119,oflow_ext_latency_ffs): altshift.tdf;
			}
		}
		lpm_ram_dq::(0,0):(16): lpm_ram_dq.tdf
		{
			altram:25:(115,5):(70,sram): altram.tdf;
		}
		pc_reg::(0,0):(12): pc_reg.vhd
		{
			lpm_add_sub:8:(22,18):(134): lpm_add_sub.tdf
			{
				addcore:9:(212,4):(58,adder): addcore.tdf;
				altshift:10:(222,2):(89,result_ext_latency_ffs): altshift.tdf;
				altshift:5:(224,2):(111,carry_ext_latency_ffs): altshift.tdf;
				altshift:5:(226,2):(119,oflow_ext_latency_ffs): altshift.tdf;
			}
		}
		mar_reg::(0,0):(8): mar_reg.vhd;
		ir_opcode::(0,0):(7): ir_opcode.vhd;
		b_reg::(0,0):(2): b_reg.vhd;
		mpychoose_reg::(0,0):(23): mpychoose_reg.vhd;
		mbr_reg::(0,0):(27): mbr_reg.vhd;
		lpm_rom::(0,0):(30): lpm_rom.tdf
		{
			altrom:28:(63,3):(70,srom): altrom.tdf;
		}
		mr_reg::(0,0):(46): mr_reg.vhd;
		counter_reg::(0,0):(48): counter_reg.vhd
		{
			lpm_add_sub:12:(21,25):(56): lpm_add_sub.tdf
			{
				addcore:13:(212,4):(49,adder): addcore.tdf;
				altshift:14:(222,2):(71,result_ext_latency_ffs): altshift.tdf;
				altshift:5:(224,2):(87,carry_ext_latency_ffs): altshift.tdf;
				altshift:5:(226,2):(95,oflow_ext_latency_ffs): altshift.tdf;
			}
		}
	}
}

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