📄 car.rpt
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24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\car.rpt
car
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\project\cpu\car.rpt
car
** EQUATIONS **
add1 : INPUT;
cin0 : INPUT;
cin1 : INPUT;
cin2 : INPUT;
cin3 : INPUT;
cin4 : INPUT;
cin5 : INPUT;
cin6 : INPUT;
cin7 : INPUT;
clk : INPUT;
load : INPUT;
reset : INPUT;
-- Node name is 'car0'
-- Equation name is 'car0', type is output
car0 = _LC5_C21;
-- Node name is 'car1'
-- Equation name is 'car1', type is output
car1 = _LC4_C21;
-- Node name is 'car2'
-- Equation name is 'car2', type is output
car2 = _LC3_C21;
-- Node name is 'car3'
-- Equation name is 'car3', type is output
car3 = _LC1_C14;
-- Node name is 'car4'
-- Equation name is 'car4', type is output
car4 = _LC6_C14;
-- Node name is 'car5'
-- Equation name is 'car5', type is output
car5 = _LC8_A23;
-- Node name is 'car6'
-- Equation name is 'car6', type is output
car6 = _LC4_A23;
-- Node name is 'car7'
-- Equation name is 'car7', type is output
car7 = _LC3_A23;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = LCELL( _EQ001);
_EQ001 = _LC3_C21 & _LC4_C21 & _LC5_C21;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = LCELL( _EQ002);
_EQ002 = _LC1_C14 & _LC4_C14 & _LC6_C14;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:149' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ003);
_EQ003 = _LC4_C21 & !_LC5_C21
# !_LC4_C21 & _LC5_C21;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ004);
_EQ004 = _LC3_C21 & !_LC4_C21
# _LC3_C21 & !_LC5_C21
# !_LC3_C21 & _LC4_C21 & _LC5_C21;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:151' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = LCELL( _EQ005);
_EQ005 = _LC1_C14 & !_LC4_C14
# !_LC1_C14 & _LC4_C14;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:152' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C14', type is buried
_LC8_C14 = LCELL( _EQ006);
_EQ006 = !_LC1_C14 & _LC6_C14
# !_LC4_C14 & _LC6_C14
# _LC1_C14 & _LC4_C14 & !_LC6_C14;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:153' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ007);
_EQ007 = !_LC2_C14 & _LC8_A23
# _LC2_C14 & !_LC8_A23;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:154' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ008);
_EQ008 = _LC4_A23 & !_LC8_A23
# !_LC2_C14 & _LC4_A23
# _LC2_C14 & !_LC4_A23 & _LC8_A23;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = LCELL( _EQ009);
_EQ009 = _LC3_A23 & !_LC8_A23
# !_LC2_C14 & _LC3_A23
# _LC3_A23 & !_LC4_A23
# _LC2_C14 & !_LC3_A23 & _LC4_A23 & _LC8_A23;
-- Node name is ':13'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = add1 & _LC7_A23 & !reset
# !add1 & _LC1_A20 & !reset;
-- Node name is ':15'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = add1 & _LC5_A23 & !reset
# !add1 & _LC6_A23 & !reset;
-- Node name is ':17'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = add1 & _LC1_A23 & !reset
# !add1 & _LC2_A23 & !reset;
-- Node name is ':19'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !add1 & _LC7_C14 & !reset
# add1 & _LC8_C14 & !reset;
-- Node name is ':21'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !add1 & _LC3_C14 & !reset
# add1 & _LC5_C14 & !reset;
-- Node name is ':23'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = add1 & _LC7_C21 & !reset
# !add1 & _LC8_C21 & !reset;
-- Node name is ':25'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !add1 & _LC2_C21 & !reset
# add1 & _LC6_C21 & !reset;
-- Node name is ':27'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = add1 & !_LC5_C21 & !reset
# !add1 & _LC1_C21 & !reset;
-- Node name is ':160'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = LCELL( _EQ018);
_EQ018 = _LC3_A23 & !load
# cin7 & load;
-- Node name is ':178'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ019);
_EQ019 = _LC4_A23 & !load
# cin6 & load;
-- Node name is ':190'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = LCELL( _EQ020);
_EQ020 = _LC8_A23 & !load
# cin5 & load;
-- Node name is ':202'
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = LCELL( _EQ021);
_EQ021 = _LC6_C14 & !load
# cin4 & load;
-- Node name is ':214'
-- Equation name is '_LC3_C14', type is buried
_LC3_C14 = LCELL( _EQ022);
_EQ022 = _LC1_C14 & !load
# cin3 & load;
-- Node name is ':226'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ023);
_EQ023 = _LC3_C21 & !load
# cin2 & load;
-- Node name is ':238'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ024);
_EQ024 = _LC4_C21 & !load
# cin1 & load;
-- Node name is ':250'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ025);
_EQ025 = _LC5_C21 & !load
# cin0 & load;
Project Information d:\project\cpu\car.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 50,249K
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