acc_alu.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity acc_alu is

	port
	(	 BR						: in 	std_logic_vector(15 downto 0);
	    add,sub,shiftl,shiftr	: in	std_logic;
        logic_and,logic_or,logic_not	: in	std_logic;
		shiftl_in,shiftr_in,reset,clk	: in	std_logic;
        accdownto0					: out	std_logic;
	    acc						: buffer 	std_logic_vector(15 downto 0)	);
	
END acc_alu;

architecture a of acc_alu is
begin
		accdownto0<='1' when acc="0000000000000000" else '0';
 	process (clk)
      variable temp : std_logic_vector(6 downto 0);
	begin	
		temp:=add & sub & shiftl & shiftr & logic_and & logic_or & logic_not;	
	    if clk'event and clk = '1' then
		   if reset='1' then
            acc<="0000000000000000"; 
           else 
             case temp is
                    when "1000000"=>    --acc=acc+br
                          acc<=acc+BR;
                    when "0100000"=>    --acc=acc-br
                          acc<=acc-BR;
                    when "0010000"=>    --shift  acc to the left 1 bit
                         acc<=acc(14 downto 0) & shiftl_in;
                    when "0001000"=>    --shift  acc to the right 1 bit
                         acc<=shiftr_in & acc(15 downto 1);
                    when "0000100"=>    --acc=acc AND br
                          acc<=acc and BR;
                    when "0000010"=>    --acc=acc OR br
                          acc<=acc or BR;
                    when "0000001"=>    -- complement acc; acc=not acc;
                          acc<=not acc;
                    when others=>NULL ;   --in other cases, acc don't be changed
              end case;
		   end if;
        end if;
	 end process;
 end a;