decoder.rpt

用VHDL编的简易CPU

-- synthesized logic cell 
_LC5_C5  = LCELL( D29);

-- Node name is 'dataout29' 
-- Equation name is 'dataout29', type is output 
dataout29 =  _LC5_C5;

-- Node name is 'dataout30~1' 
-- Equation name is 'dataout30~1', location is LC7_A14, type is buried.
-- synthesized logic cell 
_LC7_A14 = LCELL( D30);

-- Node name is 'dataout30' 
-- Equation name is 'dataout30', type is output 
dataout30 =  _LC7_A14;

-- Node name is 'dataout31~1' 
-- Equation name is 'dataout31~1', location is LC2_B14, type is buried.
-- synthesized logic cell 
_LC2_B14 = LCELL( D31);

-- Node name is 'dataout31' 
-- Equation name is 'dataout31', type is output 
dataout31 =  _LC2_B14;

-- Node name is 'flag0' 
-- Equation name is 'flag0', type is output 
flag0    =  _LC1_A10;

-- Node name is 'flag1' 
-- Equation name is 'flag1', type is output 
flag1    =  _LC4_B15;

-- Node name is ':1288' 
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = LCELL( _EQ001);
  _EQ001 =  _LC1_C2
         #  D2;

-- Node name is ':1294' 
-- Equation name is '_LC4_B7', type is buried 
_LC4_B7  = LCELL( _EQ002);
  _EQ002 =  _LC4_B7
         #  D1;

-- Node name is ':1300' 
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ003);
  _EQ003 =  _LC2_B5
         #  D0;

-- Node name is ':1347' 
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ004);
  _EQ004 =  _LC2_A14
         #  D3;

-- Node name is ':1394' 
-- Equation name is '_LC8_C14', type is buried 
_LC8_C14 = LCELL( _EQ005);
  _EQ005 =  _LC8_C14
         #  D4;

-- Node name is ':1441' 
-- Equation name is '_LC4_B22', type is buried 
_LC4_B22 = LCELL( _EQ006);
  _EQ006 =  _LC4_B22
         #  D5;

-- Node name is ':1488' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ007);
  _EQ007 =  _LC2_C16
         #  D6;

-- Node name is ':1535' 
-- Equation name is '_LC4_A17', type is buried 
_LC4_A17 = LCELL( _EQ008);
  _EQ008 =  _LC4_A17
         #  D7;

-- Node name is ':1582' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ009);
  _EQ009 =  _LC4_C21
         #  D8;

-- Node name is ':1629' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ010);
  _EQ010 =  _LC1_C10
         #  D9;

-- Node name is ':1676' 
-- Equation name is '_LC1_B21', type is buried 
_LC1_B21 = LCELL( _EQ011);
  _EQ011 =  _LC1_B21
         #  D10;

-- Node name is ':1723' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ012);
  _EQ012 =  _LC6_A2
         #  D11;

-- Node name is ':1770' 
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = LCELL( _EQ013);
  _EQ013 =  _LC2_C12
         #  D12;

-- Node name is ':1817' 
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = LCELL( _EQ014);
  _EQ014 =  _LC5_A24
         #  D13;

-- Node name is ':1864' 
-- Equation name is '_LC8_B3', type is buried 
_LC8_B3  = LCELL( _EQ015);
  _EQ015 =  _LC8_B3
         #  D14;

-- Node name is ':1911' 
-- Equation name is '_LC1_B11', type is buried 
_LC1_B11 = LCELL( _EQ016);
  _EQ016 =  _LC1_B11
         #  D15;

-- Node name is ':1958' 
-- Equation name is '_LC2_B17', type is buried 
_LC2_B17 = LCELL( _EQ017);
  _EQ017 =  _LC2_B17
         #  D16;

-- Node name is ':2005' 
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = LCELL( _EQ018);
  _EQ018 =  _LC7_C5
         #  D17;

-- Node name is ':2052' 
-- Equation name is '_LC4_B19', type is buried 
_LC4_B19 = LCELL( _EQ019);
  _EQ019 =  _LC4_B19
         #  D18;

-- Node name is ':2099' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ020);
  _EQ020 =  _LC1_A11
         #  D19;

-- Node name is ':2146' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = LCELL( _EQ021);
  _EQ021 =  _LC8_A1
         #  D20;

-- Node name is ':2193' 
-- Equation name is '_LC7_C13', type is buried 
_LC7_C13 = LCELL( _EQ022);
  _EQ022 =  _LC7_C13
         #  D21;

-- Node name is ':2308' 
-- Equation name is '_LC4_B15', type is buried 
_LC4_B15 = LCELL( _EQ023);
  _EQ023 =  _LC4_B15
         #  D23;

-- Node name is ':2314' 
-- Equation name is '_LC1_A10', type is buried 
_LC1_A10 = LCELL( _EQ024);
  _EQ024 =  _LC1_A10
         #  D24;

-- Node name is ':2361' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ025);
  _EQ025 =  _LC4_B23
         #  D22;

-- Node name is ':2408' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ026);
  _EQ026 =  _LC4_A20
         #  D25;

-- Node name is ':2455' 
-- Equation name is '_LC6_B8', type is buried 
_LC6_B8  = LCELL( _EQ027);
  _EQ027 =  _LC6_B8
         #  D26;

-- Node name is ':2502' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ028);
  _EQ028 =  _LC1_A3
         #  D27;

-- Node name is ':2549' 
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = LCELL( _EQ029);
  _EQ029 =  _LC1_C20
         #  D28;



Project Information                                 d:\project\cpu\decoder.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,487K