📄 decoder.rpt
字号:
39 - - - 21 OUTPUT 0 1 0 0 c5
27 - - C -- OUTPUT 0 1 0 0 c6
135 - - - 18 OUTPUT 0 1 0 0 c7
29 - - C -- OUTPUT 0 1 0 0 c8
83 - - C -- OUTPUT 0 1 0 0 c9
141 - - - 22 OUTPUT 0 1 0 0 c10
97 - - A -- OUTPUT 0 1 0 0 c11
60 - - - 12 OUTPUT 0 1 0 0 c12
11 - - A -- OUTPUT 0 1 0 0 c13
86 - - B -- OUTPUT 0 1 0 0 c14
17 - - B -- OUTPUT 0 1 0 0 c15
18 - - B -- OUTPUT 0 1 0 0 c16
78 - - C -- OUTPUT 0 1 0 0 c17
138 - - - 20 OUTPUT 0 1 0 0 c18
102 - - A -- OUTPUT 0 1 0 0 c19
95 - - A -- OUTPUT 0 1 0 0 c20
32 - - C -- OUTPUT 0 1 0 0 c21
144 - - - 24 OUTPUT 0 1 0 0 c22
10 - - A -- OUTPUT 0 1 0 0 c25
87 - - B -- OUTPUT 0 1 0 0 c26
113 - - - 03 OUTPUT 0 1 0 0 c27
26 - - C -- OUTPUT 0 1 0 0 c28
89 - - B -- OUTPUT 0 1 0 0 dataout0
68 - - - 07 OUTPUT 0 1 0 0 dataout1
111 - - - 02 OUTPUT 0 1 0 0 dataout2
7 - - A -- OUTPUT 0 1 0 0 dataout3
130 - - - 14 OUTPUT 0 1 0 0 dataout4
22 - - B -- OUTPUT 0 1 0 0 dataout5
131 - - - 15 OUTPUT 0 1 0 0 dataout6
133 - - - 17 OUTPUT 0 1 0 0 dataout7
33 - - C -- OUTPUT 0 1 0 0 dataout8
80 - - C -- OUTPUT 0 1 0 0 dataout9
91 - - B -- OUTPUT 0 1 0 0 dataout10
99 - - A -- OUTPUT 0 1 0 0 dataout11
122 - - - 12 OUTPUT 0 1 0 0 dataout12
13 - - A -- OUTPUT 0 1 0 0 dataout13
92 - - B -- OUTPUT 0 1 0 0 dataout14
63 - - - 11 OUTPUT 0 1 0 0 dataout15
21 - - B -- OUTPUT 0 1 0 0 dataout16
82 - - C -- OUTPUT 0 1 0 0 dataout17
42 - - - 19 OUTPUT 0 1 0 0 dataout18
62 - - - 11 OUTPUT 0 1 0 0 dataout19
110 - - - 01 OUTPUT 0 1 0 0 dataout20
49 - - - 14 OUTPUT 0 1 0 0 dataout21
143 - - - 24 OUTPUT 0 1 0 0 dataout22
19 - - B -- OUTPUT 0 1 0 0 dataout23
120 - - - 09 OUTPUT 0 1 0 0 dataout24
12 - - A -- OUTPUT 0 1 0 0 dataout25
67 - - - 08 OUTPUT 0 1 0 0 dataout26
98 - - A -- OUTPUT 0 1 0 0 dataout27
136 - - - 19 OUTPUT 0 1 0 0 dataout28
79 - - C -- OUTPUT 0 1 0 0 dataout29
14 - - A -- OUTPUT 0 1 0 0 dataout30
128 - - - 13 OUTPUT 0 1 0 0 dataout31
64 - - - 10 OUTPUT 0 1 0 0 flag0
20 - - B -- OUTPUT 0 1 0 0 flag1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\cpu\decoder.rpt
decoder
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 05 LCELL s 1 0 1 0 dataout0~1
- 8 - B 07 LCELL s 1 0 1 0 dataout1~1
- 2 - C 02 LCELL s 1 0 1 0 dataout2~1
- 1 - A 14 LCELL s 1 0 1 0 dataout3~1
- 5 - C 14 LCELL s 1 0 1 0 dataout4~1
- 5 - B 22 LCELL s 1 0 1 0 dataout5~1
- 4 - C 16 LCELL s 1 0 1 0 dataout6~1
- 1 - A 17 LCELL s 1 0 1 0 dataout7~1
- 8 - C 21 LCELL s 1 0 1 0 dataout8~1
- 3 - C 10 LCELL s 1 0 1 0 dataout9~1
- 2 - B 21 LCELL s 1 0 1 0 dataout10~1
- 4 - A 02 LCELL s 1 0 1 0 dataout11~1
- 1 - C 12 LCELL s 1 0 1 0 dataout12~1
- 6 - A 24 LCELL s 1 0 1 0 dataout13~1
- 1 - B 03 LCELL s 1 0 1 0 dataout14~1
- 2 - B 11 LCELL s 1 0 1 0 dataout15~1
- 5 - B 17 LCELL s 1 0 1 0 dataout16~1
- 2 - C 05 LCELL s 1 0 1 0 dataout17~1
- 2 - B 19 LCELL s 1 0 1 0 dataout18~1
- 2 - A 11 LCELL s 1 0 1 0 dataout19~1
- 4 - A 01 LCELL s 1 0 1 0 dataout20~1
- 2 - C 13 LCELL s 1 0 1 0 dataout21~1
- 2 - B 23 LCELL s 1 0 1 0 dataout22~1
- 3 - B 15 LCELL s 1 0 1 0 dataout23~1
- 4 - A 10 LCELL s 1 0 1 0 dataout24~1
- 6 - A 20 LCELL s 1 0 1 0 dataout25~1
- 1 - B 08 LCELL s 1 0 1 0 dataout26~1
- 5 - A 03 LCELL s 1 0 1 0 dataout27~1
- 2 - C 20 LCELL s 1 0 1 0 dataout28~1
- 5 - C 05 LCELL s 1 0 1 0 dataout29~1
- 7 - A 14 LCELL s 1 0 1 0 dataout30~1
- 2 - B 14 LCELL s 1 0 1 0 dataout31~1
- 1 - C 02 OR2 1 0 1 0 :1288
- 4 - B 07 OR2 1 0 1 0 :1294
- 2 - B 05 OR2 1 0 1 0 :1300
- 2 - A 14 OR2 1 0 1 0 :1347
- 8 - C 14 OR2 1 0 1 0 :1394
- 4 - B 22 OR2 1 0 1 0 :1441
- 2 - C 16 OR2 1 0 1 0 :1488
- 4 - A 17 OR2 1 0 1 0 :1535
- 4 - C 21 OR2 1 0 1 0 :1582
- 1 - C 10 OR2 1 0 1 0 :1629
- 1 - B 21 OR2 1 0 1 0 :1676
- 6 - A 02 OR2 1 0 1 0 :1723
- 2 - C 12 OR2 1 0 1 0 :1770
- 5 - A 24 OR2 1 0 1 0 :1817
- 8 - B 03 OR2 1 0 1 0 :1864
- 1 - B 11 OR2 1 0 1 0 :1911
- 2 - B 17 OR2 1 0 1 0 :1958
- 7 - C 05 OR2 1 0 1 0 :2005
- 4 - B 19 OR2 1 0 1 0 :2052
- 1 - A 11 OR2 1 0 1 0 :2099
- 8 - A 01 OR2 1 0 1 0 :2146
- 7 - C 13 OR2 1 0 1 0 :2193
- 4 - B 15 OR2 1 0 1 0 :2308
- 1 - A 10 OR2 1 0 1 0 :2314
- 4 - B 23 OR2 1 0 1 0 :2361
- 4 - A 20 OR2 1 0 1 0 :2408
- 6 - B 08 OR2 1 0 1 0 :2455
- 1 - A 03 OR2 1 0 1 0 :2502
- 1 - C 20 OR2 1 0 1 0 :2549
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project\cpu\decoder.rpt
decoder
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 5/ 48( 10%) 9/ 48( 18%) 4/16( 25%) 12/16( 75%) 0/16( 0%)
B: 6/ 96( 6%) 8/ 48( 16%) 8/ 48( 16%) 2/16( 12%) 12/16( 75%) 0/16( 0%)
C: 6/ 96( 6%) 7/ 48( 14%) 5/ 48( 10%) 4/16( 25%) 10/16( 62%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
08: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
12: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
19: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\decoder.rpt
decoder
** EQUATIONS **
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
D8 : INPUT;
D9 : INPUT;
D10 : INPUT;
D11 : INPUT;
D12 : INPUT;
D13 : INPUT;
D14 : INPUT;
D15 : INPUT;
D16 : INPUT;
D17 : INPUT;
D18 : INPUT;
D19 : INPUT;
D20 : INPUT;
D21 : INPUT;
D22 : INPUT;
D23 : INPUT;
D24 : INPUT;
D25 : INPUT;
D26 : INPUT;
D27 : INPUT;
D28 : INPUT;
D29 : INPUT;
D30 : INPUT;
D31 : INPUT;
-- Node name is 'C0'
-- Equation name is 'C0', type is output
C0 = _LC2_B5;
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = _LC4_B7;
-- Node name is 'C2'
-- Equation name is 'C2', type is output
C2 = _LC1_C2;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _LC2_A14;
-- Node name is 'c4'
-- Equation name is 'c4', type is output
c4 = _LC8_C14;
-- Node name is 'c5'
-- Equation name is 'c5', type is output
c5 = _LC4_B22;
-- Node name is 'c6'
-- Equation name is 'c6', type is output
c6 = _LC2_C16;
-- Node name is 'c7'
-- Equation name is 'c7', type is output
c7 = _LC4_A17;
-- Node name is 'c8'
-- Equation name is 'c8', type is output
c8 = _LC4_C21;
-- Node name is 'c9'
-- Equation name is 'c9', type is output
c9 = _LC1_C10;
-- Node name is 'c10'
-- Equation name is 'c10', type is output
c10 = _LC1_B21;
-- Node name is 'c11'
-- Equation name is 'c11', type is output
c11 = _LC6_A2;
-- Node name is 'c12'
-- Equation name is 'c12', type is output
c12 = _LC2_C12;
-- Node name is 'c13'
-- Equation name is 'c13', type is output
c13 = _LC5_A24;
-- Node name is 'c14'
-- Equation name is 'c14', type is output
c14 = _LC8_B3;
-- Node name is 'c15'
-- Equation name is 'c15', type is output
c15 = _LC1_B11;
-- Node name is 'c16'
-- Equation name is 'c16', type is output
c16 = _LC2_B17;
-- Node name is 'c17'
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