📄 b_reg.rpt
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FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\b_reg.rpt
b_reg
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: d:\project\cpu\b_reg.rpt
b_reg
** EQUATIONS **
clk : INPUT;
EN_MBR : INPUT;
MBR_IN0 : INPUT;
MBR_IN1 : INPUT;
MBR_IN2 : INPUT;
MBR_IN3 : INPUT;
MBR_IN4 : INPUT;
MBR_IN5 : INPUT;
MBR_IN6 : INPUT;
MBR_IN7 : INPUT;
MBR_IN8 : INPUT;
MBR_IN9 : INPUT;
MBR_IN10 : INPUT;
MBR_IN11 : INPUT;
MBR_IN12 : INPUT;
MBR_IN13 : INPUT;
MBR_IN14 : INPUT;
MBR_IN15 : INPUT;
-- Node name is 'BR0'
-- Equation name is 'BR0', type is output
BR0 = _LC8_A22;
-- Node name is 'BR1'
-- Equation name is 'BR1', type is output
BR1 = _LC7_B14;
-- Node name is 'BR2'
-- Equation name is 'BR2', type is output
BR2 = _LC1_B14;
-- Node name is 'BR3'
-- Equation name is 'BR3', type is output
BR3 = _LC6_B14;
-- Node name is 'BR4'
-- Equation name is 'BR4', type is output
BR4 = _LC5_B14;
-- Node name is 'BR5'
-- Equation name is 'BR5', type is output
BR5 = _LC2_B14;
-- Node name is 'BR6'
-- Equation name is 'BR6', type is output
BR6 = _LC1_A22;
-- Node name is 'BR7'
-- Equation name is 'BR7', type is output
BR7 = _LC4_A22;
-- Node name is 'BR8'
-- Equation name is 'BR8', type is output
BR8 = _LC3_B14;
-- Node name is 'BR9'
-- Equation name is 'BR9', type is output
BR9 = _LC4_B14;
-- Node name is 'BR10'
-- Equation name is 'BR10', type is output
BR10 = _LC2_A22;
-- Node name is 'BR11'
-- Equation name is 'BR11', type is output
BR11 = _LC8_B14;
-- Node name is 'BR12'
-- Equation name is 'BR12', type is output
BR12 = _LC3_A22;
-- Node name is 'BR13'
-- Equation name is 'BR13', type is output
BR13 = _LC7_A22;
-- Node name is 'BR14'
-- Equation name is 'BR14', type is output
BR14 = _LC5_A22;
-- Node name is 'BR15'
-- Equation name is 'BR15', type is output
BR15 = _LC6_A22;
-- Node name is ':19'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = EN_MBR & MBR_IN15
# !EN_MBR & _LC6_A22;
-- Node name is ':21'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = EN_MBR & MBR_IN14
# !EN_MBR & _LC5_A22;
-- Node name is ':23'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = EN_MBR & MBR_IN13
# !EN_MBR & _LC7_A22;
-- Node name is ':25'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = EN_MBR & MBR_IN12
# !EN_MBR & _LC3_A22;
-- Node name is ':27'
-- Equation name is '_LC8_B14', type is buried
_LC8_B14 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = EN_MBR & MBR_IN11
# !EN_MBR & _LC8_B14;
-- Node name is ':29'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = EN_MBR & MBR_IN10
# !EN_MBR & _LC2_A22;
-- Node name is ':31'
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = EN_MBR & MBR_IN9
# !EN_MBR & _LC4_B14;
-- Node name is ':33'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = EN_MBR & MBR_IN8
# !EN_MBR & _LC3_B14;
-- Node name is ':35'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = EN_MBR & MBR_IN7
# !EN_MBR & _LC4_A22;
-- Node name is ':37'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = EN_MBR & MBR_IN6
# !EN_MBR & _LC1_A22;
-- Node name is ':39'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = EN_MBR & MBR_IN5
# !EN_MBR & _LC2_B14;
-- Node name is ':41'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = EN_MBR & MBR_IN4
# !EN_MBR & _LC5_B14;
-- Node name is ':43'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = EN_MBR & MBR_IN3
# !EN_MBR & _LC6_B14;
-- Node name is ':45'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = EN_MBR & MBR_IN2
# !EN_MBR & _LC1_B14;
-- Node name is ':47'
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = EN_MBR & MBR_IN1
# !EN_MBR & _LC7_B14;
-- Node name is ':49'
-- Equation name is '_LC8_A22', type is buried
_LC8_A22 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = EN_MBR & MBR_IN0
# !EN_MBR & _LC8_A22;
Project Information d:\project\cpu\b_reg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,540K
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