ram.rpt

用VHDL编的简易CPU

-- Equation name is 'MBR1', type is output 
MBR1     =  _EC4_B;

-- Node name is 'MBR2' 
-- Equation name is 'MBR2', type is output 
MBR2     =  _EC2_B;

-- Node name is 'MBR3' 
-- Equation name is 'MBR3', type is output 
MBR3     =  _EC1_B;

-- Node name is 'MBR4' 
-- Equation name is 'MBR4', type is output 
MBR4     =  _EC3_B;

-- Node name is 'MBR5' 
-- Equation name is 'MBR5', type is output 
MBR5     =  _EC5_B;

-- Node name is 'MBR6' 
-- Equation name is 'MBR6', type is output 
MBR6     =  _EC6_B;

-- Node name is 'MBR7' 
-- Equation name is 'MBR7', type is output 
MBR7     =  _EC7_B;

-- Node name is 'MBR8' 
-- Equation name is 'MBR8', type is output 
MBR8     =  _EC8_B;

-- Node name is 'MBR9' 
-- Equation name is 'MBR9', type is output 
MBR9     =  _EC1_C;

-- Node name is 'MBR10' 
-- Equation name is 'MBR10', type is output 
MBR10    =  _EC5_C;

-- Node name is 'MBR11' 
-- Equation name is 'MBR11', type is output 
MBR11    =  _EC3_C;

-- Node name is 'MBR12' 
-- Equation name is 'MBR12', type is output 
MBR12    =  _EC4_C;

-- Node name is 'MBR13' 
-- Equation name is 'MBR13', type is output 
MBR13    =  _EC7_C;

-- Node name is 'MBR14' 
-- Equation name is 'MBR14', type is output 
MBR14    =  _EC6_C;

-- Node name is 'MBR15' 
-- Equation name is 'MBR15', type is output 
MBR15    =  _EC8_C;

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_0' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC2_C', type is memory 
_EC2_C   = MEMORY_SEGMENT( data0, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_1' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC4_B', type is memory 
_EC4_B   = MEMORY_SEGMENT( data1, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_2' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC2_B', type is memory 
_EC2_B   = MEMORY_SEGMENT( data2, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_3' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC1_B', type is memory 
_EC1_B   = MEMORY_SEGMENT( data3, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_4' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC3_B', type is memory 
_EC3_B   = MEMORY_SEGMENT( data4, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_5' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC5_B', type is memory 
_EC5_B   = MEMORY_SEGMENT( data5, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_6' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC6_B', type is memory 
_EC6_B   = MEMORY_SEGMENT( data6, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_7' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC7_B', type is memory 
_EC7_B   = MEMORY_SEGMENT( data7, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_8' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC8_B', type is memory 
_EC8_B   = MEMORY_SEGMENT( data8, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_9' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC1_C', type is memory 
_EC1_C   = MEMORY_SEGMENT( data9, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_10' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC5_C', type is memory 
_EC5_C   = MEMORY_SEGMENT( data10, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_11' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC3_C', type is memory 
_EC3_C   = MEMORY_SEGMENT( data11, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_12' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC4_C', type is memory 
_EC4_C   = MEMORY_SEGMENT( data12, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_13' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC7_C', type is memory 
_EC7_C   = MEMORY_SEGMENT( data13, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_14' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC6_C', type is memory 
_EC6_C   = MEMORY_SEGMENT( data14, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);

-- Node name is '|LPM_RAM_DQ:1|altram:sram|segment0_15' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC8_C', type is memory 
_EC8_C   = MEMORY_SEGMENT( data15, GLOBAL( clk), VCC, GLOBAL( c11), VCC, address0, address1, address2, address3, address4, address5, address6, address7, VCC, VCC, VCC,);



Project Information                                     d:\project\cpu\ram.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,296K