📄 ram.rpt
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Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
C: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
Total: 0 0 0 0 0 0 0 0 0 0 0 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0/16
Device-Specific Information: d:\project\cpu\ram.rpt
ram
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
7 - - - 03 INPUT 0 0 0 16 address0
5 - - - 05 INPUT 0 0 0 16 address1
35 - - - 06 INPUT 0 0 0 16 address2
38 - - - 10 INPUT 0 0 0 16 address3
43 - - - -- INPUT 0 0 0 16 address4
84 - - - -- INPUT 0 0 0 16 address5
44 - - - -- INPUT 0 0 0 16 address6
42 - - - -- INPUT 0 0 0 16 address7
1 - - - -- INPUT G 0 0 0 0 clk
2 - - - -- INPUT G 0 0 0 0 c11
62 - - C -- INPUT 0 0 0 1 data0
67 - - B -- INPUT 0 0 0 1 data1
37 - - - 09 INPUT 0 0 0 1 data2
6 - - - 04 INPUT 0 0 0 1 data3
25 - - B -- INPUT 0 0 0 1 data4
39 - - - 11 INPUT 0 0 0 1 data5
66 - - B -- INPUT 0 0 0 1 data6
21 - - B -- INPUT 0 0 0 1 data7
11 - - - 01 INPUT 0 0 0 1 data8
8 - - - 03 INPUT 0 0 0 1 data9
27 - - C -- INPUT 0 0 0 1 data10
9 - - - 02 INPUT 0 0 0 1 data11
59 - - C -- INPUT 0 0 0 1 data12
36 - - - 07 INPUT 0 0 0 1 data13
28 - - C -- INPUT 0 0 0 1 data14
30 - - C -- INPUT 0 0 0 1 data15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\project\cpu\ram.rpt
ram
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
60 - - C -- OUTPUT 0 1 0 0 MBR0
64 - - B -- OUTPUT 0 1 0 0 MBR1
69 - - A -- OUTPUT 0 1 0 0 MBR2
49 - - - 16 OUTPUT 0 1 0 0 MBR3
65 - - B -- OUTPUT 0 1 0 0 MBR4
17 - - A -- OUTPUT 0 1 0 0 MBR5
50 - - - 17 OUTPUT 0 1 0 0 MBR6
24 - - B -- OUTPUT 0 1 0 0 MBR7
80 - - - 23 OUTPUT 0 1 0 0 MBR8
61 - - C -- OUTPUT 0 1 0 0 MBR9
18 - - A -- OUTPUT 0 1 0 0 MBR10
22 - - B -- OUTPUT 0 1 0 0 MBR11
29 - - C -- OUTPUT 0 1 0 0 MBR12
58 - - C -- OUTPUT 0 1 0 0 MBR13
71 - - A -- OUTPUT 0 1 0 0 MBR14
23 - - B -- OUTPUT 0 1 0 0 MBR15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\cpu\ram.rpt
ram
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 2 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_0
- - 4 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_1
- - 2 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_2
- - 1 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_3
- - 3 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_4
- - 5 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_5
- - 6 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_6
- - 7 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_7
- - 8 B -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_8
- - 1 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_9
- - 5 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_10
- - 3 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_11
- - 4 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_12
- - 7 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_13
- - 6 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_14
- - 8 C -- MEM_SGMT 9 0 1 0 |LPM_RAM_DQ:1|altram:sram|segment0_15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project\cpu\ram.rpt
ram
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 11/ 96( 11%) 10/ 48( 20%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 12/ 96( 12%) 7/ 48( 14%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\ram.rpt
ram
** EQUATIONS **
address0 : INPUT;
address1 : INPUT;
address2 : INPUT;
address3 : INPUT;
address4 : INPUT;
address5 : INPUT;
address6 : INPUT;
address7 : INPUT;
clk : INPUT;
c11 : INPUT;
data0 : INPUT;
data1 : INPUT;
data2 : INPUT;
data3 : INPUT;
data4 : INPUT;
data5 : INPUT;
data6 : INPUT;
data7 : INPUT;
data8 : INPUT;
data9 : INPUT;
data10 : INPUT;
data11 : INPUT;
data12 : INPUT;
data13 : INPUT;
data14 : INPUT;
data15 : INPUT;
-- Node name is 'MBR0'
-- Equation name is 'MBR0', type is output
MBR0 = _EC2_C;
-- Node name is 'MBR1'
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