📄 test1.rpt
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Device-Specific Information: d:\project\cpu\test1.rpt
test1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
20 - - D -- OUTPUT 0 1 0 0 c0
19 - - D -- OUTPUT 0 1 0 0 c1
22 - - D -- OUTPUT 0 1 0 0 c2
87 - - E -- OUTPUT 0 1 0 0 c3
86 - - E -- OUTPUT 0 1 0 0 c4
27 - - E -- OUTPUT 0 1 0 0 c5
28 - - E -- OUTPUT 0 1 0 0 c6
29 - - E -- OUTPUT 0 1 0 0 c7
51 - - - 14 OUTPUT 0 1 0 0 c8
78 - - F -- OUTPUT 0 1 0 0 c9
32 - - F -- OUTPUT 0 1 0 0 c10
33 - - F -- OUTPUT 0 1 0 0 c11
30 - - F -- OUTPUT 0 1 0 0 c12
80 - - F -- OUTPUT 0 1 0 0 c13
31 - - F -- OUTPUT 0 1 0 0 c14
12 - - C -- OUTPUT 0 1 0 0 c15
98 - - B -- OUTPUT 0 1 0 0 c16
101 - - A -- OUTPUT 0 1 0 0 c17
144 - - A -- OUTPUT 0 1 0 0 c18
100 - - A -- OUTPUT 0 1 0 0 c19
7 - - A -- OUTPUT 0 1 0 0 c20
92 - - C -- OUTPUT 0 1 0 0 c21
8 - - A -- OUTPUT 0 1 0 0 c22
102 - - A -- OUTPUT 0 1 0 0 c23
79 - - F -- OUTPUT 0 1 0 0 c24
23 - - D -- OUTPUT 0 1 0 0 c25
97 - - B -- OUTPUT 0 1 0 0 c26
9 - - B -- OUTPUT 0 1 0 0 c27
88 - - D -- OUTPUT 0 1 0 0 c28
82 - - E -- OUTPUT 0 1 0 0 c29
135 - - - 19 OUTPUT 0 1 0 0 c30
18 - - D -- OUTPUT 0 1 0 0 c31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\cpu\test1.rpt
test1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - D 01 OR2 0 3 0 8 |BL:13|:104
- 6 - D 01 OR2 0 3 0 9 |BL:13|:116
- 4 - D 01 OR2 0 3 0 8 |BL:13|:128
- 3 - D 06 AND2 s ! 1 1 0 5 |BL:13|~187~1
- 7 - D 06 OR2 ! 3 1 0 3 |BL:13|:187
- 6 - D 06 AND2 s ! 2 1 0 5 |BL:13|~196~1
- 5 - D 06 AND2 s ! 2 1 0 6 |BL:13|~205~1
- 4 - D 06 OR2 s 2 1 0 3 |BL:13|~223~1
- 2 - D 03 AND2 3 1 0 2 |BL:13|:250
- 2 - D 06 AND2 3 1 0 2 |BL:13|:259
- 3 - D 03 OR2 ! 1 1 0 1 |BL:13|:268
- 5 - D 02 AND2 3 1 0 2 |BL:13|:290
- 8 - D 02 AND2 s 3 1 0 4 |BL:13|~304~1
- 8 - D 06 AND2 s 4 0 0 2 |BL:13|~343~1
- 7 - D 02 AND2 2 1 0 2 |BL:13|:343
- 6 - D 02 OR2 s 1 2 0 2 |BL:13|~413~1
- 1 - D 09 OR2 0 2 0 1 |BL:13|:473
- 1 - D 06 AND2 s ! 0 1 0 3 |BL:13|~497~1
- 6 - D 09 OR2 0 4 0 1 |BL:13|:497
- 3 - D 02 OR2 1 2 0 3 |BL:13|:518
- 5 - D 10 OR2 0 4 0 1 |BL:13|:541
- 6 - D 10 OR2 1 2 0 1 |BL:13|:553
- 7 - D 10 OR2 1 3 0 1 |BL:13|:554
- 4 - D 02 OR2 2 2 0 1 |BL:13|:578
- 5 - D 03 OR2 0 4 0 1 |BL:13|:592
- 6 - D 03 OR2 1 2 0 1 |BL:13|:604
- 7 - D 03 OR2 1 3 0 1 |BL:13|:610
- 1 - D 04 AND2 0 3 0 4 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:125
- 5 - D 01 AND2 0 3 0 2 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:133
- 7 - D 11 OR2 0 2 0 1 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:149
- 5 - D 11 OR2 0 3 0 1 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:150
- 5 - D 04 OR2 0 3 0 1 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:152
- 3 - D 10 OR2 0 4 0 1 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:153
- 2 - D 01 OR2 0 3 0 1 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:154
- 5 - D 09 OR2 0 4 0 1 |CAR:3|LPM_ADD_SUB:102|addcore:adder|:155
- 2 - D 09 DFFE + 0 4 0 34 |CAR:3|:13
- 7 - D 01 DFFE + 0 4 0 35 |CAR:3|:15
- 1 - D 10 DFFE + 0 4 0 36 |CAR:3|:17
- 1 - D 03 DFFE + 0 4 0 36 |CAR:3|:19
- 1 - D 01 DFFE + 0 2 0 36 |CAR:3|:21
- 1 - D 11 DFFE + 0 4 0 35 |CAR:3|:23
- 2 - D 11 DFFE + 0 4 0 36 |CAR:3|:25
- 4 - D 11 DFFE + 0 3 0 35 |CAR:3|:27
- 4 - D 09 OR2 0 3 0 1 |CAR:3|:160
- 3 - D 09 OR2 0 4 0 1 |CAR:3|:161
- 7 - D 09 OR2 0 4 0 1 |CAR:3|:178
- 2 - D 10 AND2 s 0 2 0 1 |CAR:3|~179~1
- 4 - D 10 OR2 s 1 3 0 3 |CAR:3|~179~2
- 8 - D 10 OR2 0 4 0 1 |CAR:3|:190
- 8 - D 03 OR2 0 4 0 1 |CAR:3|:202
- 8 - D 01 OR2 0 4 0 1 |CAR:3|:217
- 3 - D 11 OR2 0 3 0 1 |CAR:3|:226
- 4 - D 03 OR2 s ! 0 2 0 2 |CAR:3|~227~1
- 1 - D 08 OR2 s ! 0 2 0 3 |CAR:3|~227~2
- 2 - D 02 OR2 s ! 2 1 0 4 |CAR:3|~227~3
- 1 - D 02 OR2 s 1 3 0 1 |CAR:3|~227~4
- 8 - D 09 AND2 0 4 0 2 |CAR:3|:227
- 6 - D 11 OR2 0 3 0 1 |CAR:3|:238
- - 6 D -- MEM_SGMT 0 8 1 3 |LPM_ROM:1|altrom:srom|segment0_0
- - 8 D -- MEM_SGMT 0 8 1 3 |LPM_ROM:1|altrom:srom|segment0_1
- - 5 D -- MEM_SGMT 0 8 1 3 |LPM_ROM:1|altrom:srom|segment0_2
- - 1 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_3
- - 8 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_4
- - 4 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_5
- - 2 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_6
- - 5 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_7
- - 3 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_8
- - 3 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_9
- - 4 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_10
- - 6 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_11
- - 1 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_12
- - 2 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_13
- - 7 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_14
- - 8 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_15
- - 5 F -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_16
- - 4 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_17
- - 5 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_18
- - 2 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_19
- - 8 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_20
- - 7 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_21
- - 3 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_22
- - 6 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_23
- - 1 A -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_24
- - 2 D -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_25
- - 7 D -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_26
- - 1 D -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_27
- - 4 D -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_28
- - 7 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_29
- - 6 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_30
- - 3 D -- MEM_SGMT 0 8 1 0 |LPM_ROM:1|altrom:srom|segment0_31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project\cpu\test1.rpt
test1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 20/ 96( 20%) 33/ 48( 68%) 0/ 48( 0%) 2/16( 12%) 6/16( 37%) 0/16( 0%)
E: 8/ 96( 8%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
F: 9/ 96( 9%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\test1.rpt
test1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\project\cpu\test1.rpt
test1
** EQUATIONS **
clk : INPUT;
downto0 : INPUT;
flag0 : INPUT;
flag1 : INPUT;
mpyadd : INPUT;
mpyshift : INPUT;
mpysub : INPUT;
opcode0 : INPUT;
opcode1 : INPUT;
opcode2 : INPUT;
opcode3 : INPUT;
opcode4 : INPUT;
opcode5 : INPUT;
opcode6 : INPUT;
opcode7 : INPUT;
-- Node name is 'c0'
-- Equation name is 'c0', type is output
c0 = _EC6_D;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _EC8_D;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _EC5_D;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _EC1_E;
-- Node name is 'c4'
-- Equation name is 'c4', type is output
c4 = _EC8_E;
-- Node name is 'c5'
-- Equation name is 'c5', type is output
c5 = _EC4_E;
-- Node name is 'c6'
-- Equation name is 'c6', type is output
c6 = _EC2_E;
-- Node name is 'c7'
-- Equation name is 'c7', type is output
c7 = _EC5_E;
-- Node name is 'c8'
-- Equation name is 'c8', type is output
c8 = _EC3_E;
-- Node name is 'c9'
-- Equation name is 'c9', type is output
c9 = _EC3_F;
-- Node name is 'c10'
-- Equation name is 'c10', type is output
c10 = _EC4_F;
-- Node name is 'c11'
-- Equation name is 'c11', type is output
c11 = _EC6_F;
-- Node name is 'c12'
-- Equation name is 'c12', type is output
c12 = _EC1_F;
-- Node name is 'c13'
-- Equation name is 'c13', type is output
c13 = _EC2_F;
-- Node name is 'c14'
-- Equation name is 'c14', type is output
c14 = _EC7_F;
-- Node name is 'c15'
-- Equation name is 'c15', type is output
c15 = _EC8_F;
-- Node name is 'c16'
-- Equation name is 'c16', type is output
c16 = _EC5_F;
-- Node name is 'c17'
-- Equation name is 'c17', type is output
c17 = _EC4_A;
-- Node name is 'c18'
-- Equation name is 'c18', type is output
c18 = _EC5_A;
-- Node name is 'c19'
-- Equation name is 'c19', type is output
c19 = _EC2_A;
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