mpychoose_reg.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Mpychoose_Reg is
port(
	 MR_In: in std_logic_vector(15 downto 0);
	 Mpyadd,Mpysub,Mpyshiftr: out std_logic;
	 Q1: in std_logic;
	 clk: in std_logic
	 );
end Mpychoose_Reg;

architecture a of Mpychoose_Reg is
begin
	process(clk)
	 variable temp:std_logic_vector(1 downto 0);
	 begin
	    temp:=MR_In(0)&Q1;
		if(clk'event and clk='1')then
			if(temp="10")then
				Mpysub<='1';
				Mpyadd<='0';
				Mpyshiftr<='0';
			elsif(temp="01")then
				Mpyadd<='1';
				Mpysub<='0';
				Mpyshiftr<='0';
			elsif(temp="00" or temp="11")then
				Mpyshiftr<='1';
				Mpyadd<='0';
				Mpysub<='0';
			end if;
		end if;
	end process;
end a;