📄 pc_reg.rpt
字号:
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\pc_reg.rpt
pc_reg
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\project\cpu\pc_reg.rpt
pc_reg
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 reset
Device-Specific Information: d:\project\cpu\pc_reg.rpt
pc_reg
** EQUATIONS **
clk : INPUT;
EN_MBR : INPUT;
increase1 : INPUT;
MBR_IN0 : INPUT;
MBR_IN1 : INPUT;
MBR_IN2 : INPUT;
MBR_IN3 : INPUT;
MBR_IN4 : INPUT;
MBR_IN5 : INPUT;
MBR_IN6 : INPUT;
MBR_IN7 : INPUT;
reset : INPUT;
-- Node name is 'PC0'
-- Equation name is 'PC0', type is output
PC0 = _LC6_B23;
-- Node name is 'PC1'
-- Equation name is 'PC1', type is output
PC1 = _LC7_B15;
-- Node name is 'PC2'
-- Equation name is 'PC2', type is output
PC2 = _LC1_B15;
-- Node name is 'PC3'
-- Equation name is 'PC3', type is output
PC3 = _LC3_A24;
-- Node name is 'PC4'
-- Equation name is 'PC4', type is output
PC4 = _LC8_A24;
-- Node name is 'PC5'
-- Equation name is 'PC5', type is output
PC5 = _LC1_A24;
-- Node name is 'PC6'
-- Equation name is 'PC6', type is output
PC6 = _LC5_B15;
-- Node name is 'PC7'
-- Equation name is 'PC7', type is output
PC7 = _LC3_B15;
-- Node name is '|LPM_ADD_SUB:134|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ001);
_EQ001 = _LC1_B15 & _LC6_B23 & _LC7_B15;
-- Node name is '|LPM_ADD_SUB:134|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ002);
_EQ002 = _LC2_B23 & _LC3_A24;
-- Node name is '|LPM_ADD_SUB:134|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ003);
_EQ003 = _LC1_A24 & _LC2_B23 & _LC3_A24 & _LC8_A24;
-- Node name is ':13'
-- Equation name is '_LC3_B15', type is buried
_LC3_B15 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = !EN_MBR & _LC8_B15
# EN_MBR & MBR_IN7;
-- Node name is ':15'
-- Equation name is '_LC5_B15', type is buried
_LC5_B15 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = !EN_MBR & _LC6_B15
# EN_MBR & MBR_IN6;
-- Node name is ':17'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = !EN_MBR & _LC7_A24
# EN_MBR & MBR_IN5;
-- Node name is ':19'
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = !EN_MBR & _LC5_A24
# EN_MBR & MBR_IN4;
-- Node name is ':21'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ008 = !EN_MBR & _LC4_A24
# EN_MBR & MBR_IN3;
-- Node name is ':23'
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = DFFE( _EQ009, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ009 = !EN_MBR & _LC4_B15
# EN_MBR & MBR_IN2;
-- Node name is ':25'
-- Equation name is '_LC7_B15', type is buried
_LC7_B15 = DFFE( _EQ010, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ010 = !EN_MBR & _LC2_B15
# EN_MBR & MBR_IN1;
-- Node name is ':27'
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = DFFE( _EQ011, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ011 = !EN_MBR & !increase1 & _LC6_B23
# !EN_MBR & increase1 & !_LC6_B23
# EN_MBR & MBR_IN0;
-- Node name is ':160'
-- Equation name is '_LC8_B15', type is buried
_LC8_B15 = LCELL( _EQ012);
_EQ012 = _LC3_B15 & !_LC5_B15
# !_LC2_A24 & _LC3_B15
# increase1 & _LC2_A24 & !_LC3_B15 & _LC5_B15
# !increase1 & _LC3_B15;
-- Node name is ':172'
-- Equation name is '_LC6_B15', type is buried
_LC6_B15 = LCELL( _EQ013);
_EQ013 = !_LC2_A24 & _LC5_B15
# increase1 & _LC2_A24 & !_LC5_B15
# !increase1 & _LC5_B15;
-- Node name is ':181'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ014);
_EQ014 = _LC1_A24 & !_LC6_A24
# _LC1_A24 & !_LC8_A24
# increase1 & !_LC1_A24 & _LC6_A24 & _LC8_A24
# !increase1 & _LC1_A24;
-- Node name is ':190'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ015);
_EQ015 = !_LC3_A24 & _LC8_A24
# !_LC2_B23 & _LC8_A24
# increase1 & _LC2_B23 & _LC3_A24 & !_LC8_A24
# !increase1 & _LC8_A24;
-- Node name is ':199'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ016);
_EQ016 = !_LC2_B23 & _LC3_A24
# increase1 & _LC2_B23 & !_LC3_A24
# !increase1 & _LC3_A24;
-- Node name is ':208'
-- Equation name is '_LC4_B15', type is buried
_LC4_B15 = LCELL( _EQ017);
_EQ017 = _LC1_B15 & !_LC7_B15
# _LC1_B15 & !_LC6_B23
# increase1 & !_LC1_B15 & _LC6_B23 & _LC7_B15
# !increase1 & _LC1_B15;
-- Node name is ':217'
-- Equation name is '_LC2_B15', type is buried
_LC2_B15 = LCELL( _EQ018);
_EQ018 = !_LC6_B23 & _LC7_B15
# increase1 & _LC6_B23 & !_LC7_B15
# !increase1 & _LC7_B15;
Project Information d:\project\cpu\pc_reg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,819K
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