📄 cpu.rpt
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Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 32/96 ( 33%)
Total logic cells used: 377/1152 ( 32%)
Total embedded cells used: 48/48 (100%)
Total EABs used: 6/6 (100%)
Average fan-in: 3.25/4 ( 81%)
Total fan-in: 1229/4608 ( 26%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 377
Total flipflops required: 106
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 26/1152 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 1 0 0 8 0 8 1 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 26/8
B: 8 1 4 8 8 2 1 8 8 8 6 8 8 8 6 0 8 8 8 8 3 0 0 7 8 134/8
C: 0 0 8 8 7 5 3 8 7 7 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 61/8
D: 3 0 7 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 10/8
E: 0 5 8 8 8 8 8 8 2 7 8 7 8 8 0 0 8 8 8 8 8 6 7 0 8 146/8
F: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
Total: 19 7 27 24 31 15 20 25 17 22 14 23 48 16 6 0 16 16 16 16 11 6 7 7 16 377/48
Device-Specific Information: d:\project1\cpu\cpu.rpt
cpu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\project1\cpu\cpu.rpt
cpu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
92 - - C -- OUTPUT 0 1 0 0 c0
14 - - C -- OUTPUT 0 1 0 0 c1
90 - - C -- OUTPUT 0 1 0 0 c2
27 - - E -- OUTPUT 0 1 0 0 c3
83 - - E -- OUTPUT 0 1 0 0 c4
98 - - B -- OUTPUT 0 1 0 0 c5
96 - - B -- OUTPUT 0 1 0 0 c6
87 - - E -- OUTPUT 0 1 0 0 c7
10 - - B -- OUTPUT 0 1 0 0 c8
19 - - D -- OUTPUT 0 1 0 0 c9
95 - - B -- OUTPUT 0 1 0 0 c10
102 - - A -- OUTPUT 0 1 0 0 c11
82 - - E -- OUTPUT 0 1 0 0 c12
31 - - F -- OUTPUT 0 1 0 0 c13
12 - - C -- OUTPUT 0 1 0 0 c14
9 - - B -- OUTPUT 0 1 0 0 c15
18 - - D -- OUTPUT 0 1 0 0 c16
88 - - D -- OUTPUT 0 1 0 0 c17
86 - - E -- OUTPUT 0 1 0 0 c18
13 - - C -- OUTPUT 0 1 0 0 c19
101 - - A -- OUTPUT 0 1 0 0 c20
97 - - B -- OUTPUT 0 1 0 0 c21
79 - - F -- OUTPUT 0 1 0 0 c22
89 - - C -- OUTPUT 0 1 0 0 c23
28 - - E -- OUTPUT 0 1 0 0 c24
22 - - D -- OUTPUT 0 1 0 0 c25
144 - - A -- OUTPUT 0 1 0 0 c26
20 - - D -- OUTPUT 0 1 0 0 c27
23 - - D -- OUTPUT 0 1 0 0 c28
8 - - A -- OUTPUT 0 1 0 0 c29
132 - - - 16 OUTPUT 0 1 0 0 c30
33 - - F -- OUTPUT 0 1 0 0 c31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project1\cpu\cpu.rpt
cpu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 10 OR2 0 4 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry1
- 1 - B 12 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry2
- 5 - B 17 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry3
- 7 - B 13 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry4
- 2 - B 24 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry5
- 6 - B 24 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry6
- 2 - E 16 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry7
- 1 - E 16 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry8
- 2 - E 21 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry9
- 2 - E 20 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry10
- 2 - E 07 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry11
- 1 - E 07 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry12
- 8 - E 06 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry13
- 6 - E 10 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|pcarry14
- 7 - B 05 OR2 0 2 0 2 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:161
- 8 - B 10 OR2 0 4 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:178
- 8 - B 12 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:179
- 8 - B 17 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:180
- 8 - B 16 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:181
- 8 - B 19 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:182
- 8 - B 24 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:183
- 6 - E 18 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:184
- 8 - E 16 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:185
- 8 - E 17 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:186
- 8 - E 20 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:187
- 8 - E 24 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:188
- 8 - E 07 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:189
- 7 - E 06 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:190
- 7 - E 05 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:191
- 7 - E 10 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:372|addcore:adder|:192
- 1 - B 05 OR2 0 4 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry1
- 2 - B 12 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry2
- 1 - B 17 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry3
- 4 - B 19 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry4
- 2 - B 19 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry5
- 4 - B 24 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry6
- 8 - E 18 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry7
- 2 - E 17 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry8
- 4 - E 17 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry9
- 3 - E 24 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry10
- 2 - E 24 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry11
- 3 - E 06 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry12
- 1 - E 06 OR2 0 3 0 2 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry13
- 1 - E 10 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|pcarry14
- 6 - B 10 OR2 0 4 0 1 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|:178
- 6 - B 12 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|:179
- 6 - B 17 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|:180
- 6 - B 16 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|:181
- 6 - B 19 OR2 0 3 0 1 |ACC_ALU:49|LPM_ADD_SUB:485|addcore:adder|:182
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