📄 cpu.rpt
字号:
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S G G G G V S S S S S S S S S S S S S
E E E E G E E E E V E E E G E N N N N C E E E E E E E V E E E E E E
R R R R N R R R R C R R R N R D D D D C R R R R R R R C R R R R R R
c V V V V D V V V V C V c V V D V I I I I I V V V V V V V C V V V V V V
2 E E E E I E E E E I E 3 E E I E N N N N N E E E E E E E I E E E E E E
6 D D D D O D D D D O D 0 D D O D T T T T T D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | c11
c29 | 8 101 | c20
c15 | 9 100 | RESERVED
c8 | 10 99 | RESERVED
RESERVED | 11 98 | c5
c14 | 12 97 | c21
c19 | 13 96 | c6
c1 | 14 95 | c10
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | c0
c16 | 18 91 | RESERVED
c9 | 19 EPF10K20TC144-3 90 | c2
c27 | 20 89 | c23
RESERVED | 21 88 | c17
c25 | 22 87 | c7
c28 | 23 86 | c18
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | c4
c3 | 27 82 | c12
c24 | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | c22
c13 | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
c31 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R G R V V G c G G G R R V R R R R G R R R R V R
E E E N E E E E C E E E E N E C C N l N N N E E C E E E E N E E E E C E
S S S D S S S S C S S S S D S C C D k D D D S S C S S S S D S S S S C S
E E E I E E E E I E E E E I E I I I I I I E E I E E E E I E E E E I E
R R R O R R R R O R R R R O R N N N N N N R R O R R R R O R R R R O R
V V V V V V V V V V V V T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\project1\cpu\cpu.rpt
cpu
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
A2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A5 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
A7 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
B2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B3 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
B4 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 11/22( 50%)
B5 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
B6 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
B7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B8 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
B9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 13/22( 59%)
B10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
B11 6/ 8( 75%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
B12 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
B13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
B14 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
B16 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
B17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
B18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
B19 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
B20 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
B23 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 12/22( 54%)
B24 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
C3 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
C4 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
C5 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C6 5/ 8( 62%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
C7 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
C8 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
C9 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
C10 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
C12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
D1 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D3 7/ 8( 87%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
E2 5/ 8( 62%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
E3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
E4 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 14/22( 63%)
E5 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
E6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
E7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
E8 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 18/22( 81%)
E9 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
E10 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
E11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
E12 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
E13 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
E16 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
E17 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
E18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
E19 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
E20 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
E21 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
E22 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
E24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 7/8 ( 87%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
B25 8/8 (100%) 1/8 ( 12%) 7/8 ( 87%) 0/2 2/2 17/22( 77%)
C25 8/8 (100%) 8/8 (100%) 5/8 ( 62%) 0/2 2/2 8/22( 36%)
D25 8/8 (100%) 5/8 ( 62%) 7/8 ( 87%) 0/2 2/2 8/22( 36%)
E25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 0/2 2/2 17/22( 77%)
F25 8/8 (100%) 5/8 ( 62%) 5/8 ( 62%) 0/2 2/2 8/22( 36%)
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