📄 acc_alu.rpt
字号:
acc_alu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 accdownto0
18 - - A -- OUTPUT 0 1 0 0 acc0
17 - - A -- OUTPUT 0 1 0 0 acc1
16 - - A -- OUTPUT 0 1 0 0 acc2
71 - - A -- OUTPUT 0 1 0 0 acc3
72 - - A -- OUTPUT 0 1 0 0 acc4
70 - - A -- OUTPUT 0 1 0 0 acc5
73 - - A -- OUTPUT 0 1 0 0 acc6
51 - - - 18 OUTPUT 0 1 0 0 acc7
58 - - C -- OUTPUT 0 1 0 0 acc8
62 - - C -- OUTPUT 0 1 0 0 acc9
61 - - C -- OUTPUT 0 1 0 0 acc10
59 - - C -- OUTPUT 0 1 0 0 acc11
48 - - - 15 OUTPUT 0 1 0 0 acc12
79 - - - 24 OUTPUT 0 1 0 0 acc13
81 - - - 22 OUTPUT 0 1 0 0 acc14
83 - - - 13 OUTPUT 0 1 0 0 acc15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project1\cpu\acc_alu.rpt
acc_alu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 07 OR2 2 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry1
- 8 - A 19 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry2
- 7 - A 20 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry3
- 3 - A 20 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry4
- 6 - A 21 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry5
- 8 - A 21 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry6
- 6 - A 24 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry7
- 1 - A 24 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry8
- 6 - C 16 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry9
- 8 - C 16 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry10
- 4 - C 21 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry11
- 5 - B 23 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry12
- 8 - B 23 OR2 1 2 0 2 |LPM_ADD_SUB:372|addcore:adder|pcarry13
- 6 - B 14 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|pcarry14
- 7 - A 01 OR2 1 1 0 1 |LPM_ADD_SUB:372|addcore:adder|:161
- 7 - A 07 OR2 2 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:178
- 5 - A 19 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:179
- 7 - A 17 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:180
- 8 - A 20 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:181
- 8 - A 13 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:182
- 7 - A 21 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:183
- 8 - A 18 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:184
- 8 - A 24 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:185
- 7 - C 24 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:186
- 7 - C 16 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:187
- 8 - C 21 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:188
- 8 - B 16 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:189
- 7 - B 23 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:190
- 8 - B 22 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:191
- 7 - B 14 OR2 1 2 0 1 |LPM_ADD_SUB:372|addcore:adder|:192
- 4 - A 07 OR2 2 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry1
- 3 - A 17 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry2
- 8 - A 17 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry3
- 1 - A 13 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry4
- 7 - A 13 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry5
- 2 - A 18 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry6
- 4 - A 18 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry7
- 2 - C 24 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry8
- 8 - C 24 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry9
- 1 - C 21 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry10
- 6 - C 21 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry11
- 1 - B 23 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry12
- 4 - B 23 OR2 1 2 0 2 |LPM_ADD_SUB:485|addcore:adder|pcarry13
- 1 - B 14 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|pcarry14
- 2 - A 07 OR2 s 2 1 0 1 |LPM_ADD_SUB:485|addcore:adder|~178~1
- 3 - A 19 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:179
- 5 - A 17 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:180
- 1 - A 20 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:181
- 2 - A 13 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:182
- 2 - A 21 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:183
- 3 - A 18 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:184
- 2 - A 24 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:185
- 3 - C 24 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:186
- 3 - C 16 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:187
- 2 - C 21 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:188
- 1 - B 16 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:189
- 2 - B 23 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:190
- 2 - B 22 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:191
- 2 - B 14 OR2 1 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:192
- 8 - B 14 DFFE + 1 3 1 6 :29
- 1 - B 22 DFFE + 1 3 1 9 :31
- 6 - B 23 DFFE + 1 3 1 9 :33
- 4 - B 16 DFFE + 1 3 1 9 :35
- 5 - C 21 DFFE + 1 3 1 9 :37
- 2 - C 16 DFFE + 1 3 1 9 :39
- 1 - C 24 DFFE + 1 3 1 9 :41
- 7 - A 24 DFFE + 1 3 1 9 :43
- 1 - A 18 DFFE + 1 3 1 9 :45
- 1 - A 21 DFFE + 1 3 1 9 :47
- 5 - A 13 DFFE + 1 3 1 9 :49
- 2 - A 20 DFFE + 1 3 1 9 :51
- 4 - A 17 DFFE + 1 3 1 9 :53
- 1 - A 19 DFFE + 1 3 1 9 :55
- 3 - A 07 DFFE + 1 3 1 9 :57
- 5 - A 01 DFFE + 1 3 1 10 :59
- 3 - B 17 AND2 s 4 0 0 3 ~1141~1
- 6 - B 13 AND2 3 1 0 16 :1141
- 8 - B 13 OR2 ! 3 1 0 16 :1159
- 5 - B 13 OR2 1 3 0 1 :1162
- 3 - B 13 AND2 3 1 0 16 :1177
- 2 - B 13 OR2 1 3 0 1 :1180
- 5 - B 17 AND2 s 4 0 0 1 ~1195~1
- 6 - B 17 AND2 3 1 0 16 :1195
- 3 - B 14 OR2 1 2 0 1 :1198
- 2 - B 17 AND2 3 1 0 16 :1213
- 4 - B 14 OR2 0 3 0 1 :1216
- 4 - B 17 AND2 3 1 0 16 :1231
- 5 - B 14 OR2 0 3 0 1 :1234
- 7 - B 17 AND2 s 4 0 0 3 ~1249~1
- 1 - B 17 AND2 3 1 0 16 :1249
- 3 - B 22 OR2 1 3 0 1 :1261
- 4 - B 22 OR2 1 3 0 1 :1264
- 5 - B 22 OR2 0 3 0 1 :1267
- 6 - B 22 OR2 0 3 0 1 :1270
- 7 - B 22 OR2 0 3 0 1 :1273
- 4 - B 13 OR2 1 3 0 1 :1285
- 1 - B 13 OR2 1 3 0 1 :1288
- 2 - B 20 OR2 0 3 0 1 :1291
- 1 - B 20 OR2 0 3 0 1 :1294
- 3 - B 23 OR2 0 3 0 1 :1297
- 2 - B 16 OR2 1 3 0 1 :1309
- 3 - B 16 OR2 1 3 0 1 :1312
- 5 - B 16 OR2 0 3 0 1 :1315
- 6 - B 16 OR2 0 3 0 1 :1318
- 7 - B 16 OR2 0 3 0 1 :1321
- 7 - C 13 OR2 1 3 0 1 :1333
- 8 - C 13 OR2 1 3 0 1 :1336
- 2 - C 13 OR2 0 3 0 1 :1339
- 3 - C 21 OR2 0 3 0 1 :1342
- 7 - C 21 OR2 0 3 0 1 :1345
- 4 - C 13 OR2 1 3 0 1 :1357
- 6 - C 13 OR2 1 3 0 1 :1360
- 5 - C 13 OR2 0 3 0 1 :1363
- 4 - C 16 OR2 0 3 0 1 :1366
- 5 - C 16 OR2 0 3 0 1 :1369
- 3 - C 13 OR2 1 3 0 1 :1381
- 1 - C 13 OR2 1 3 0 1 :1384
- 4 - C 24 OR2 0 3 0 1 :1387
- 5 - C 24 OR2 0 3 0 1 :1390
- 6 - C 24 OR2 0 3 0 1 :1393
- 8 - A 14 OR2 1 3 0 1 :1405
- 4 - A 14 OR2 1 3 0 1 :1408
- 3 - A 24 OR2 0 3 0 1 :1411
- 4 - A 24 OR2 0 3 0 1 :1414
- 5 - A 24 OR2 0 3 0 1 :1417
- 6 - A 14 OR2 1 3 0 1 :1429
- 2 - A 14 OR2 1 3 0 1 :1432
- 5 - A 18 OR2 0 3 0 1 :1435
- 6 - A 18 OR2 0 3 0 1 :1438
- 7 - A 18 OR2 0 3 0 1 :1441
- 4 - A 16 OR2 1 3 0 1 :1453
- 1 - A 16 OR2 1 3 0 1 :1456
- 3 - A 21 OR2 0 3 0 1 :1459
- 4 - A 21 OR2 0 3 0 1 :1462
- 5 - A 21 OR2 0 3 0 1 :1465
- 5 - A 14 OR2 1 3 0 1 :1477
- 7 - A 14 OR2 1 3 0 1 :1480
- 3 - A 13 OR2 0 3 0 1 :1483
- 4 - A 13 OR2 0 3 0 1 :1486
- 6 - A 13 OR2 0 3 0 1 :1489
- 1 - A 14 OR2 1 3 0 1 :1501
- 3 - A 14 OR2 1 3 0 1 :1504
- 4 - A 20 OR2 0 3 0 1 :1507
- 5 - A 20 OR2 0 3 0 1 :1510
- 6 - A 20 OR2 0 3 0 1 :1513
- 3 - A 16 OR2 1 3 0 1 :1525
- 2 - A 16 OR2 1 3 0 1 :1528
- 1 - A 17 OR2 0 3 0 1 :1531
- 2 - A 17 OR2 0 3 0 1 :1534
- 6 - A 17 OR2 0 3 0 1 :1537
- 2 - A 19 OR2 1 3 0 1 :1549
- 6 - A 19 OR2 1 3 0 1 :1552
- 1 - A 15 OR2 0 3 0 1 :1555
- 2 - A 15 OR2 0 3 0 1 :1558
- 4 - A 19 OR2 0 3 0 1 :1561
- 2 - A 11 OR2 1 3 0 1 :1573
- 3 - A 11 OR2 1 3 0 1 :1576
- 1 - A 11 OR2 0 3 0 1 :1579
- 1 - A 07 OR2 0 3 0 1 :1582
- 6 - A 07 OR2 0 4 0 1 :1585
- 1 - A 01 OR2 1 3 0 1 :1597
- 2 - A 01 OR2 1 3 0 1 :1600
- 3 - A 01 OR2 0 3 0 1 :1603
- 4 - A 01 OR2 1 2 0 1 :1606
- 6 - A 01 OR2 1 3 0 1 :1609
- 5 - A 16 AND2 s 0 4 0 1 ~1884~1
- 1 - C 16 AND2 s 0 4 0 1 ~1884~2
- 6 - A 16 AND2 s 0 4 0 1 ~1884~3
- 7 - A 16 AND2 s 0 4 0 1 ~1884~4
- 8 - A 16 AND2 0 4 1 0 :1884
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project1\cpu\acc_alu.rpt
acc_alu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 23/ 96( 23%) 6/ 48( 12%) 24/ 48( 50%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
B: 14/ 96( 14%) 0/ 48( 0%) 19/ 48( 39%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
C: 7/ 96( 7%) 0/ 48( 0%) 18/ 48( 37%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 4/24( 16%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project1\cpu\acc_alu.rpt
acc_alu
** CLOCK SIGNALS **
Type Fan-out Name
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