bl.rpt

用VHDL编的简易CPU

-- Equation name is '~378~1', location is LC5_B15, type is buried.
-- synthesized logic cell 
_LC5_B15 = LCELL( _EQ022);
  _EQ022 =  _LC1_C19 &  opcode4 &  opcode5;

-- Node name is ':389' 
-- Equation name is '_LC6_B17', type is buried 
_LC6_B17 = LCELL( _EQ023);
  _EQ023 = !accdownto0 &  _LC5_B15 &  opcode6 &  opcode7;

-- Node name is '~459~1' 
-- Equation name is '~459~1', location is LC6_B16, type is buried.
-- synthesized logic cell 
!_LC6_B16 = _LC6_B16~NOT;
_LC6_B16~NOT = LCELL( _EQ024);
  _EQ024 = !_LC4_B18 & !_LC5_B18;

-- Node name is '~503~1' 
-- Equation name is '~503~1', location is LC1_B15, type is buried.
-- synthesized logic cell 
_LC1_B15 = LCELL( _EQ025);
  _EQ025 =  _LC2_B15 &  opcode6
         #  _LC2_B15 &  opcode7
         #  _LC2_B15 & !_LC7_B15;

-- Node name is '~503~2' 
-- Equation name is '~503~2', location is LC3_B16, type is buried.
-- synthesized logic cell 
_LC3_B16 = LCELL( _EQ026);
  _EQ026 = !_LC1_B14 &  _LC1_B15 & !_LC2_B14;

-- Node name is ':503' 
-- Equation name is '_LC3_B17', type is buried 
_LC3_B17 = LCELL( _EQ027);
  _EQ027 =  _LC3_B16 &  _LC4_B17
         #  _LC3_B16 &  _LC4_B13
         #  _LC3_B16 & !_LC4_B16;

-- Node name is ':510' 
-- Equation name is '_LC8_B17', type is buried 
_LC8_B17 = LCELL( _EQ028);
  _EQ028 =  _LC5_B15 &  opcode6 &  opcode7;

-- Node name is '~525~1' 
-- Equation name is '~525~1', location is LC6_B13, type is buried.
-- synthesized logic cell 
!_LC6_B13 = _LC6_B13~NOT;
_LC6_B13~NOT = LCELL( _EQ029);
  _EQ029 = !_LC1_B13
         # !mpyshift & !mpysub;

-- Node name is ':525' 
-- Equation name is '_LC1_B17', type is buried 
_LC1_B17 = LCELL( _EQ030);
  _EQ030 = !_LC8_B13 &  _LC8_B17
         #  _LC6_B13
         #  _LC4_B13;

-- Node name is '~542~1' 
-- Equation name is '~542~1', location is LC2_B18, type is buried.
-- synthesized logic cell 
_LC2_B18 = LCELL( _EQ031);
  _EQ031 = !_LC2_B13 & !_LC7_B18;

-- Node name is ':542' 
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = LCELL( _EQ032);
  _EQ032 =  _LC1_B17 &  _LC2_B18 & !_LC4_B18 & !_LC5_B18;

-- Node name is '~549~1' 
-- Equation name is '~549~1', location is LC2_B14, type is buried.
-- synthesized logic cell 
!_LC2_B14 = _LC2_B14~NOT;
_LC2_B14~NOT = LCELL( _EQ033);
  _EQ033 = !_LC1_B18 & !_LC7_B15
         # !_LC1_B18 & !opcode6
         # !_LC1_B18 &  opcode7;

-- Node name is '~549~2' 
-- Equation name is '~549~2', location is LC1_B14, type is buried.
-- synthesized logic cell 
!_LC1_B14 = _LC1_B14~NOT;
_LC1_B14~NOT = LCELL( _EQ034);
  _EQ034 = !_LC6_B15 & !opcode6
         # !_LC6_B15 &  opcode7
         # !_LC5_B15 & !_LC6_B15;

-- Node name is '~560~1' 
-- Equation name is '~560~1', location is LC2_B15, type is buried.
-- synthesized logic cell 
_LC2_B15 = LCELL( _EQ035);
  _EQ035 = !_LC8_B15 &  opcode6
         # !_LC8_B15 &  opcode7
         # !_LC5_B15 & !_LC8_B15;

-- Node name is ':560' 
-- Equation name is '_LC1_B16', type is buried 
_LC1_B16 = LCELL( _EQ036);
  _EQ036 =  _LC1_B14 &  _LC1_B15
         #  _LC1_B15 &  _LC2_B14
         #  _LC1_B15 &  _LC8_B16;

-- Node name is ':576' 
-- Equation name is '_LC5_B16', type is buried 
_LC5_B16 = LCELL( _EQ037);
  _EQ037 =  _LC4_B17
         #  _LC4_B13;

-- Node name is ':599' 
-- Equation name is '_LC7_B16', type is buried 
_LC7_B16 = LCELL( _EQ038);
  _EQ038 =  _LC5_B16 & !_LC6_B13 & !_LC6_B16
         # !_LC2_B18 & !_LC6_B16;

-- Node name is ':612' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = LCELL( _EQ039);
  _EQ039 = !_LC2_B14 &  _LC7_B16
         #  _LC1_B14 & !_LC2_B14
         # !_LC2_B15;

-- Node name is ':617' 
-- Equation name is '_LC3_B15', type is buried 
_LC3_B15 = LCELL( _EQ040);
  _EQ040 =  _LC2_B16 &  opcode6
         #  _LC2_B16 &  opcode7
         #  _LC2_B16 & !_LC7_B15;

-- Node name is ':630' 
-- Equation name is '_LC4_B17', type is buried 
_LC4_B17 = LCELL( _EQ041);
  _EQ041 =  _LC8_B17
         #  _LC8_B13;

-- Node name is ':636' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = LCELL( _EQ042);
  _EQ042 =  _LC1_B13 &  mpysub
         # !_LC4_B13 &  _LC4_B17;

-- Node name is ':642' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = LCELL( _EQ043);
  _EQ043 =  _LC7_B13 & !mpyshift
         # !_LC1_B13 &  _LC7_B13
         #  _LC2_B13;

-- Node name is ':656' 
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = LCELL( _EQ044);
  _EQ044 =  _LC3_B13 & !_LC5_B18 & !_LC7_B18
         #  _LC4_B18 & !_LC5_B18;

-- Node name is ':660' 
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ045);
  _EQ045 =  _LC4_B14
         #  _LC5_B14 & !_LC6_B15
         # !_LC6_B15 &  _LC8_B18;

-- Node name is ':672' 
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = LCELL( _EQ046);
  _EQ046 =  _LC7_B15 & !opcode6 & !opcode7
         #  _LC7_B14;

-- Node name is ':674' 
-- Equation name is '_LC7_B14', type is buried 
_LC7_B14 = LCELL( _EQ047);
  _EQ047 =  _LC3_B14 & !_LC8_B15
         # !_LC1_B18 &  _LC6_B14 & !_LC8_B15;

-- Node name is ':744' 
-- Equation name is '_LC8_B13', type is buried 
_LC8_B13 = LCELL( _EQ048);
  _EQ048 =  flag0 &  _LC1_B21
         #  downto0 &  flag1 &  _LC1_B21;

-- Node name is '~788~1' 
-- Equation name is '~788~1', location is LC5_B17, type is buried.
-- synthesized logic cell 
_LC5_B17 = LCELL( _EQ049);
  _EQ049 =  _LC3_B16 & !_LC4_B13;

-- Node name is ':788' 
-- Equation name is '_LC2_B17', type is buried 
_LC2_B17 = LCELL( _EQ050);
  _EQ050 =  _LC3_B16 & !_LC4_B13 &  _LC4_B16 &  _LC8_B13;

-- Node name is '~845~1' 
-- Equation name is '~845~1', location is LC4_B16, type is buried.
-- synthesized logic cell 
_LC4_B16 = LCELL( _EQ051);
  _EQ051 =  _LC2_B18 & !_LC4_B18 & !_LC5_B18 & !_LC6_B13;

-- Node name is ':845' 
-- Equation name is '_LC7_B17', type is buried 
_LC7_B17 = LCELL( _EQ052);
  _EQ052 =  _LC4_B16 &  _LC5_B17 &  _LC8_B13
         #  _LC4_B16 &  _LC5_B17 &  _LC6_B17;

-- Node name is ':902' 
-- Equation name is '_LC5_B13', type is buried 
_LC5_B13 = LCELL( _EQ053);
  _EQ053 =  downto0 & !flag0 &  flag1 &  _LC1_B21;



Project Information                                     d:\project1\cpu\bl.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,336K