📄 bl.rpt
字号:
- 1 - B 14 OR2 s ! 2 2 0 3 ~549~2
- 2 - B 15 OR2 s 2 2 0 2 ~560~1
- 1 - B 16 OR2 0 4 1 0 :560
- 5 - B 16 OR2 0 2 0 1 :576
- 7 - B 16 OR2 0 4 0 1 :599
- 2 - B 16 OR2 0 4 0 1 :612
- 3 - B 15 OR2 2 2 1 0 :617
- 4 - B 17 OR2 0 2 0 3 :630
- 7 - B 13 OR2 1 3 0 1 :636
- 3 - B 13 OR2 1 3 0 1 :642
- 8 - B 18 OR2 0 4 0 1 :656
- 6 - B 14 OR2 0 4 0 1 :660
- 8 - B 14 OR2 2 2 1 0 :672
- 7 - B 14 OR2 0 4 0 1 :674
- 8 - B 13 OR2 3 1 0 4 :744
- 5 - B 17 AND2 s 0 2 0 1 ~788~1
- 2 - B 17 AND2 0 4 1 0 :788
- 4 - B 16 AND2 s 0 4 0 3 ~845~1
- 7 - B 17 OR2 0 4 1 0 :845
- 5 - B 13 AND2 3 1 1 0 :902
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project1\cpu\bl.rpt
bl
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
B: 10/ 96( 10%) 0/ 48( 0%) 26/ 48( 54%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project1\cpu\bl.rpt
bl
** EQUATIONS **
accdownto0 : INPUT;
C0 : INPUT;
C1 : INPUT;
C2 : INPUT;
downto0 : INPUT;
flag0 : INPUT;
flag1 : INPUT;
mpyadd : INPUT;
mpyshift : INPUT;
mpysub : INPUT;
opcode0 : INPUT;
opcode1 : INPUT;
opcode2 : INPUT;
opcode3 : INPUT;
opcode4 : INPUT;
opcode5 : INPUT;
opcode6 : INPUT;
opcode7 : INPUT;
-- Node name is 'address0'
-- Equation name is 'address0', type is output
address0 = _LC5_B13;
-- Node name is 'address1'
-- Equation name is 'address1', type is output
address1 = _LC7_B17;
-- Node name is 'address2'
-- Equation name is 'address2', type is output
address2 = _LC2_B17;
-- Node name is 'address3'
-- Equation name is 'address3', type is output
address3 = GND;
-- Node name is 'address4'
-- Equation name is 'address4', type is output
address4 = _LC8_B14;
-- Node name is 'address5'
-- Equation name is 'address5', type is output
address5 = _LC3_B15;
-- Node name is 'address6'
-- Equation name is 'address6', type is output
address6 = _LC1_B16;
-- Node name is 'address7'
-- Equation name is 'address7', type is output
address7 = _LC3_B17;
-- Node name is 'add1car'
-- Equation name is 'add1car', type is output
add1car = _LC4_A19;
-- Node name is 'loadcar'
-- Equation name is 'loadcar', type is output
loadcar = _LC5_A19;
-- Node name is 'resetcar'
-- Equation name is 'resetcar', type is output
resetcar = _LC3_A19;
-- Node name is ':105'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = LCELL( _EQ001);
_EQ001 = !C1 & !C2 & _LC4_A19
# C0;
-- Node name is ':117'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ002);
_EQ002 = !C0 & !C2 & _LC5_A19
# !C0 & C1;
-- Node name is ':129'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = LCELL( _EQ003);
_EQ003 = !C0 & !C1 & _LC3_A19
# !C0 & !C1 & C2;
-- Node name is ':206'
-- Equation name is '_LC8_B15', type is buried
!_LC8_B15 = _LC8_B15~NOT;
_LC8_B15~NOT = LCELL( _EQ004);
_EQ004 = opcode6
# opcode7
# !_LC4_B15;
-- Node name is ':215'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ005);
_EQ005 = _LC5_B15 & !opcode6 & !opcode7;
-- Node name is ':224'
-- Equation name is '_LC1_B18', type is buried
!_LC1_B18 = _LC1_B18~NOT;
_LC1_B18~NOT = LCELL( _EQ006);
_EQ006 = !_LC1_C19
# opcode4
# opcode5
# _LC3_B18;
-- Node name is '~233~1'
-- Equation name is '~233~1', location is LC3_B18, type is buried.
-- synthesized logic cell
_LC3_B18 = LCELL( _EQ007);
_EQ007 = !opcode6
# opcode7;
-- Node name is ':233'
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ008);
_EQ008 = _LC7_B15 & opcode6 & !opcode7;
-- Node name is ':242'
-- Equation name is '_LC6_B15', type is buried
!_LC6_B15 = _LC6_B15~NOT;
_LC6_B15~NOT = LCELL( _EQ009);
_EQ009 = !_LC4_B15
# !opcode6
# opcode7;
-- Node name is ':251'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ010);
_EQ010 = _LC5_B15 & opcode6 & !opcode7;
-- Node name is '~260~1'
-- Equation name is '~260~1', location is LC6_B18, type is buried.
-- synthesized logic cell
!_LC6_B18 = _LC6_B18~NOT;
_LC6_B18~NOT = LCELL( _EQ011);
_EQ011 = opcode6
# !opcode7;
-- Node name is ':260'
-- Equation name is '_LC5_B18', type is buried
!_LC5_B18 = _LC5_B18~NOT;
_LC5_B18~NOT = LCELL( _EQ012);
_EQ012 = !_LC6_B18
# !_LC1_C19
# opcode4
# opcode5;
-- Node name is '~269~1'
-- Equation name is '~269~1', location is LC7_B15, type is buried.
-- synthesized logic cell
!_LC7_B15 = _LC7_B15~NOT;
_LC7_B15~NOT = LCELL( _EQ013);
_EQ013 = !_LC1_C19
# !opcode4
# opcode5;
-- Node name is ':269'
-- Equation name is '_LC4_B18', type is buried
!_LC4_B18 = _LC4_B18~NOT;
_LC4_B18~NOT = LCELL( _EQ014);
_EQ014 = !_LC6_B18
# !_LC7_B15;
-- Node name is '~278~1'
-- Equation name is '~278~1', location is LC4_B15, type is buried.
-- synthesized logic cell
!_LC4_B15 = _LC4_B15~NOT;
_LC4_B15~NOT = LCELL( _EQ015);
_EQ015 = !_LC1_C19
# opcode4
# !opcode5;
-- Node name is ':278'
-- Equation name is '_LC7_B18', type is buried
!_LC7_B18 = _LC7_B18~NOT;
_LC7_B18~NOT = LCELL( _EQ016);
_EQ016 = !_LC1_C19
# opcode4
# !opcode5
# !_LC6_B18;
-- Node name is ':303'
-- Equation name is '_LC2_B13', type is buried
!_LC2_B13 = _LC2_B13~NOT;
_LC2_B13~NOT = LCELL( _EQ017);
_EQ017 = !_LC1_B21
# downto0
# flag0
# flag1;
-- Node name is '~345~1'
-- Equation name is '~345~1', location is LC1_C19, type is buried.
-- synthesized logic cell
_LC1_C19 = LCELL( _EQ018);
_EQ018 = !opcode0 & !opcode1 & !opcode2 & !opcode3;
-- Node name is '~345~2'
-- Equation name is '~345~2', location is LC1_B13, type is buried.
-- synthesized logic cell
!_LC1_B13 = _LC1_B13~NOT;
_LC1_B13~NOT = LCELL( _EQ019);
_EQ019 = !_LC1_B21
# downto0
# !flag1;
-- Node name is ':345'
-- Equation name is '_LC4_B13', type is buried
!_LC4_B13 = _LC4_B13~NOT;
_LC4_B13~NOT = LCELL( _EQ020);
_EQ020 = !_LC1_B13
# !mpyadd;
-- Node name is '~356~1'
-- Equation name is '~356~1', location is LC1_B21, type is buried.
-- synthesized logic cell
_LC1_B21 = LCELL( _EQ021);
_EQ021 = _LC5_B15 & !opcode6 & opcode7;
-- Node name is '~378~1'
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