📄 mr_reg.rpt
字号:
48 - - - 15 OUTPUT 0 1 0 0 MR12
59 - - C -- OUTPUT 0 1 0 0 MR13
61 - - C -- OUTPUT 0 1 0 0 MR14
62 - - C -- OUTPUT 0 1 0 0 MR15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project1\cpu\mr_reg.rpt
mr_reg
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 15 DFFE + 2 1 1 2 :21
- 3 - C 15 DFFE + 2 1 1 2 :23
- 5 - C 15 DFFE + 2 1 1 2 :25
- 2 - C 15 DFFE + 2 1 1 2 :27
- 6 - B 18 DFFE + 2 1 1 2 :29
- 1 - B 18 DFFE + 2 1 1 2 :31
- 2 - B 18 DFFE + 2 1 1 2 :33
- 3 - B 18 DFFE + 2 1 1 2 :35
- 1 - A 10 DFFE + 2 1 1 2 :37
- 2 - A 10 DFFE + 2 1 1 2 :39
- 6 - A 10 DFFE + 2 1 1 2 :41
- 3 - A 10 DFFE + 2 1 1 2 :43
- 2 - C 12 DFFE + 2 1 1 2 :45
- 1 - C 12 DFFE + 2 1 1 2 :47
- 5 - C 12 DFFE + 2 1 1 2 :49
- 6 - C 12 DFFE + 2 1 1 1 :51
- 8 - C 15 OR2 2 1 0 1 :292
- 7 - C 15 OR2 1 2 0 1 :304
- 6 - C 15 OR2 1 2 0 1 :313
- 4 - C 15 OR2 1 2 0 1 :322
- 8 - B 18 OR2 1 2 0 1 :331
- 7 - B 18 OR2 1 2 0 1 :340
- 5 - B 18 OR2 1 2 0 1 :349
- 4 - B 18 OR2 1 2 0 1 :358
- 8 - A 10 OR2 1 2 0 1 :367
- 7 - A 10 OR2 1 2 0 1 :376
- 5 - A 10 OR2 1 2 0 1 :385
- 4 - A 10 OR2 1 2 0 1 :394
- 8 - C 12 OR2 1 2 0 1 :403
- 7 - C 12 OR2 1 2 0 1 :412
- 4 - C 12 OR2 1 2 0 1 :421
- 3 - C 12 OR2 1 2 0 1 :430
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project1\cpu\mr_reg.rpt
mr_reg
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 3/ 48( 6%) 0/ 48( 0%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 4/ 48( 8%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
C: 4/ 96( 4%) 5/ 48( 10%) 5/ 48( 10%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project1\cpu\mr_reg.rpt
mr_reg
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: d:\project1\cpu\mr_reg.rpt
mr_reg
** EQUATIONS **
clk : INPUT;
EN_MBR : INPUT;
MBR_In0 : INPUT;
MBR_In1 : INPUT;
MBR_In2 : INPUT;
MBR_In3 : INPUT;
MBR_In4 : INPUT;
MBR_In5 : INPUT;
MBR_In6 : INPUT;
MBR_In7 : INPUT;
MBR_In8 : INPUT;
MBR_In9 : INPUT;
MBR_In10 : INPUT;
MBR_In11 : INPUT;
MBR_In12 : INPUT;
MBR_In13 : INPUT;
MBR_In14 : INPUT;
MBR_In15 : INPUT;
shiftr : INPUT;
shiftr_in : INPUT;
-- Node name is 'MR0'
-- Equation name is 'MR0', type is output
MR0 = _LC6_C12;
-- Node name is 'MR1'
-- Equation name is 'MR1', type is output
MR1 = _LC5_C12;
-- Node name is 'MR2'
-- Equation name is 'MR2', type is output
MR2 = _LC1_C12;
-- Node name is 'MR3'
-- Equation name is 'MR3', type is output
MR3 = _LC2_C12;
-- Node name is 'MR4'
-- Equation name is 'MR4', type is output
MR4 = _LC3_A10;
-- Node name is 'MR5'
-- Equation name is 'MR5', type is output
MR5 = _LC6_A10;
-- Node name is 'MR6'
-- Equation name is 'MR6', type is output
MR6 = _LC2_A10;
-- Node name is 'MR7'
-- Equation name is 'MR7', type is output
MR7 = _LC1_A10;
-- Node name is 'MR8'
-- Equation name is 'MR8', type is output
MR8 = _LC3_B18;
-- Node name is 'MR9'
-- Equation name is 'MR9', type is output
MR9 = _LC2_B18;
-- Node name is 'MR10'
-- Equation name is 'MR10', type is output
MR10 = _LC1_B18;
-- Node name is 'MR11'
-- Equation name is 'MR11', type is output
MR11 = _LC6_B18;
-- Node name is 'MR12'
-- Equation name is 'MR12', type is output
MR12 = _LC2_C15;
-- Node name is 'MR13'
-- Equation name is 'MR13', type is output
MR13 = _LC5_C15;
-- Node name is 'MR14'
-- Equation name is 'MR14', type is output
MR14 = _LC3_C15;
-- Node name is 'MR15'
-- Equation name is 'MR15', type is output
MR15 = _LC1_C15;
-- Node name is ':21'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !EN_MBR & _LC8_C15
# EN_MBR & MBR_In15;
-- Node name is ':23'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !EN_MBR & _LC7_C15
# EN_MBR & MBR_In14;
-- Node name is ':25'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !EN_MBR & _LC6_C15
# EN_MBR & MBR_In13;
-- Node name is ':27'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !EN_MBR & _LC4_C15
# EN_MBR & MBR_In12;
-- Node name is ':29'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !EN_MBR & _LC8_B18
# EN_MBR & MBR_In11;
-- Node name is ':31'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !EN_MBR & _LC7_B18
# EN_MBR & MBR_In10;
-- Node name is ':33'
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