📄 mbr_reg.rpt
字号:
22 - - B -- OUTPUT 0 1 0 0 q1
65 - - B -- OUTPUT 0 1 0 0 q2
78 - - - 24 OUTPUT 0 1 0 0 q3
69 - - A -- OUTPUT 0 1 0 0 q4
73 - - A -- OUTPUT 0 1 0 0 q5
48 - - - 15 OUTPUT 0 1 0 0 q6
70 - - A -- OUTPUT 0 1 0 0 q7
58 - - C -- OUTPUT 0 1 0 0 q8
62 - - C -- OUTPUT 0 1 0 0 q9
59 - - C -- OUTPUT 0 1 0 0 q10
24 - - B -- OUTPUT 0 1 0 0 q11
25 - - B -- OUTPUT 0 1 0 0 q12
21 - - B -- OUTPUT 0 1 0 0 q13
3 - - - 12 OUTPUT 0 1 0 0 q14
61 - - C -- OUTPUT 0 1 0 0 q15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 21 DFFE + 2 1 1 1 :36
- 3 - B 11 DFFE + 2 1 1 1 :38
- 1 - B 11 DFFE + 2 1 1 1 :40
- 8 - B 11 DFFE + 2 1 1 1 :42
- 6 - B 11 DFFE + 2 1 1 1 :44
- 5 - C 21 DFFE + 2 1 1 1 :46
- 1 - C 21 DFFE + 2 1 1 1 :48
- 7 - C 21 DFFE + 2 1 1 1 :50
- 5 - A 15 DFFE + 2 1 1 1 :52
- 3 - A 15 DFFE + 2 1 1 1 :54
- 1 - A 15 DFFE + 2 1 1 1 :56
- 8 - A 15 DFFE + 2 1 1 1 :58
- 2 - B 24 DFFE + 2 1 1 1 :60
- 8 - B 24 DFFE + 2 1 1 1 :62
- 1 - B 24 DFFE + 2 1 1 1 :64
- 6 - B 24 DFFE + 2 1 1 1 :66
- 8 - C 21 OR2 2 1 0 1 :243
- 7 - B 11 OR2 2 1 0 1 :255
- 5 - B 11 OR2 2 1 0 1 :264
- 4 - B 11 OR2 2 1 0 1 :273
- 2 - B 11 OR2 2 1 0 1 :282
- 6 - C 21 OR2 2 1 0 1 :291
- 4 - C 21 OR2 2 1 0 1 :300
- 2 - C 21 OR2 2 1 0 1 :309
- 7 - A 15 OR2 2 1 0 1 :318
- 6 - A 15 OR2 2 1 0 1 :327
- 4 - A 15 OR2 2 1 0 1 :336
- 2 - A 15 OR2 2 1 0 1 :345
- 7 - B 24 OR2 2 1 0 1 :354
- 5 - B 24 OR2 2 1 0 1 :363
- 4 - B 24 OR2 2 1 0 1 :372
- 3 - B 24 OR2 2 1 0 1 :381
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 0/ 48( 0%) 4/ 48( 8%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 6/ 96( 6%) 8/ 48( 16%) 4/ 48( 8%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 6/ 48( 12%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** EQUATIONS **
ACC_IN0 : INPUT;
ACC_IN1 : INPUT;
ACC_IN2 : INPUT;
ACC_IN3 : INPUT;
ACC_IN4 : INPUT;
ACC_IN5 : INPUT;
ACC_IN6 : INPUT;
ACC_IN7 : INPUT;
ACC_IN8 : INPUT;
ACC_IN9 : INPUT;
ACC_IN10 : INPUT;
ACC_IN11 : INPUT;
ACC_IN12 : INPUT;
ACC_IN13 : INPUT;
ACC_IN14 : INPUT;
ACC_IN15 : INPUT;
clk : INPUT;
EN_ACC : INPUT;
RAM_IN0 : INPUT;
RAM_IN1 : INPUT;
RAM_IN2 : INPUT;
RAM_IN3 : INPUT;
RAM_IN4 : INPUT;
RAM_IN5 : INPUT;
RAM_IN6 : INPUT;
RAM_IN7 : INPUT;
RAM_IN8 : INPUT;
RAM_IN9 : INPUT;
RAM_IN10 : INPUT;
RAM_IN11 : INPUT;
RAM_IN12 : INPUT;
RAM_IN13 : INPUT;
RAM_IN14 : INPUT;
RAM_IN15 : INPUT;
READ_RAM : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC6_B24;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC1_B24;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC8_B24;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC2_B24;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC8_A15;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC1_A15;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC3_A15;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = _LC5_A15;
-- Node name is 'q8'
-- Equation name is 'q8', type is output
q8 = _LC7_C21;
-- Node name is 'q9'
-- Equation name is 'q9', type is output
q9 = _LC1_C21;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = _LC5_C21;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = _LC6_B11;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = _LC8_B11;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = _LC1_B11;
-- Node name is 'q14'
-- Equation name is 'q14', type is output
q14 = _LC3_B11;
-- Node name is 'q15'
-- Equation name is 'q15', type is output
q15 = _LC3_C21;
-- Node name is ':36'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC8_C21 & !READ_RAM
# RAM_IN15 & READ_RAM;
-- Node name is ':38'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC7_B11 & !READ_RAM
# RAM_IN14 & READ_RAM;
-- Node name is ':40'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC5_B11 & !READ_RAM
# RAM_IN13 & READ_RAM;
-- Node name is ':42'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC4_B11 & !READ_RAM
# RAM_IN12 & READ_RAM;
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