📄 mbr_reg.rpt
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Project Information d:\project\cpu\mbr_reg.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/19/2008 23:41:07
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MBR_REG
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
mbr_reg EPF10K10LC84-3 35 16 0 0 0 % 32 5 %
User Pins: 35 16 0
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
***** Logic for device 'mbr_reg' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** ERROR SUMMARY **
Info: Chip 'mbr_reg' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
C
R R R R A R A A O
E E E A C E C R R C R N
S S S M C S C V E A A G C A F
E E E _ _ E _ C N M M N _ M _ ^
R R R I I R I C _ _ _ D I _ # D n
V V V N N V N I q A c I I I N I T O C
E E E 1 1 E 1 N 1 C l N N N 1 q N q C N E
D D D 2 3 D 2 T 4 C k 0 2 T 5 0 5 3 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | q5
^nCE | 14 72 | ACC_IN5
#TDI | 15 71 | RAM_IN7
RAM_IN4 | 16 70 | q7
ACC_IN4 | 17 69 | q4
ACC_IN7 | 18 68 | GNDINT
RAM_IN6 | 19 67 | ACC_IN2
VCCINT | 20 66 | RAM_IN11
q13 | 21 65 | q2
q1 | 22 EPF10K10LC84-3 64 | RAM_IN14
ACC_IN3 | 23 63 | VCCINT
q11 | 24 62 | q9
q12 | 25 61 | q15
GNDINT | 26 60 | RAM_IN15
RAM_IN8 | 27 59 | q10
ACC_IN8 | 28 58 | q8
RAM_IN10 | 29 57 | #TMS
ACC_IN10 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R A R A R V G R A A V G R q R R A R A
C n E C E C A C N E C C C N A 6 A E C A C
C C S C S C M C D A C C C D M M S C M C
I O E _ E _ _ I I D _ _ I I _ _ E _ _ _
N N R I R I I N N _ I I N N I I R I I I
T F V N V N N T T R N N T T N N V N N N
I E 1 E 1 1 A 1 0 3 9 E 9 1 6
G D 1 D 4 3 M D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
B11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
B24 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
C21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 45/53 ( 84%)
Total logic cells used: 32/576 ( 5%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.00/4 ( 75%)
Total fan-in: 96/2304 ( 4%)
Total input pins required: 35
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 32
Total flipflops required: 16
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8/0
B: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 8 16/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 8/0
Total: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 8 0 0 8 32/0
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
44 - - - -- INPUT 0 0 0 1 ACC_IN0
43 - - - -- INPUT 0 0 0 1 ACC_IN1
67 - - B -- INPUT 0 0 0 1 ACC_IN2
23 - - B -- INPUT 0 0 0 1 ACC_IN3
17 - - A -- INPUT 0 0 0 1 ACC_IN4
72 - - A -- INPUT 0 0 0 1 ACC_IN5
53 - - - 20 INPUT 0 0 0 1 ACC_IN6
18 - - A -- INPUT 0 0 0 1 ACC_IN7
28 - - C -- INPUT 0 0 0 1 ACC_IN8
51 - - - 18 INPUT 0 0 0 1 ACC_IN9
30 - - C -- INPUT 0 0 0 1 ACC_IN10
36 - - - 07 INPUT 0 0 0 1 ACC_IN11
5 - - - 05 INPUT 0 0 0 1 ACC_IN12
7 - - - 03 INPUT 0 0 0 1 ACC_IN13
38 - - - 10 INPUT 0 0 0 1 ACC_IN14
81 - - - 22 INPUT 0 0 0 1 ACC_IN15
1 - - - -- INPUT G 0 0 0 0 clk
2 - - - -- INPUT 0 0 0 16 EN_ACC
84 - - - -- INPUT 0 0 0 1 RAM_IN0
52 - - - 19 INPUT 0 0 0 1 RAM_IN1
83 - - - 13 INPUT 0 0 0 1 RAM_IN2
47 - - - 14 INPUT 0 0 0 1 RAM_IN3
16 - - A -- INPUT 0 0 0 1 RAM_IN4
79 - - - 24 INPUT 0 0 0 1 RAM_IN5
19 - - A -- INPUT 0 0 0 1 RAM_IN6
71 - - A -- INPUT 0 0 0 1 RAM_IN7
27 - - C -- INPUT 0 0 0 1 RAM_IN8
49 - - - 16 INPUT 0 0 0 1 RAM_IN9
29 - - C -- INPUT 0 0 0 1 RAM_IN10
66 - - B -- INPUT 0 0 0 1 RAM_IN11
8 - - - 03 INPUT 0 0 0 1 RAM_IN12
39 - - - 11 INPUT 0 0 0 1 RAM_IN13
64 - - B -- INPUT 0 0 0 1 RAM_IN14
60 - - C -- INPUT 0 0 0 1 RAM_IN15
42 - - - -- INPUT 0 0 0 16 READ_RAM
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\project\cpu\mbr_reg.rpt
mbr_reg
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - 23 OUTPUT 0 1 0 0 q0
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