📄 ms32pci.vhd
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-- Reads single DWORD from memory space!
procedure RDSW(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable read_data : Data_buffer;
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd := "0110";
address(1 downto 0) := "00";
Vec2Hex (address,str_8,Good2);
report "Read single DWORD from memory space! Address : "&str_8 ;
READ_WRITE(address,data,1,bus_cmd,bus_sel,'1');
end RDSW;
--------------------------------------------------------------------------
-- Procedure implements instruction WRMW --
--------------------------------------------------------------------------
-- Writes multiple DWORDs to memory space - burst mode
procedure WRMW(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd := "1111";
address(1 downto 0) := "10";
Vec2Hex (address,str_8,Good2);
report "Write multiple DWORDs to memory space! Address : "&str_8 ;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'0');
end WRMW;
--------------------------------------------------------------------------
-- Procedure implements instruction RDMW --
--------------------------------------------------------------------------
-- Reads multiple DWORDs from memory space - burst mode
procedure RDMW(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable read_data : Data_buffer;
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd := "1100";
address(1 downto 0) := "10";
Vec2Hex (address,str_8,Good2);
report "Read multiple DWORDs from memory space! Address : "&str_8;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'1');
end RDMW;
--------------------------------------------------------------------------
-- Procedure implements instruction RDML --
--------------------------------------------------------------------------
-- Reads multiple DWORDs from memory space!
procedure RDML(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd: STD_LOGIC_VECTOR(3 downto 0);
variable read_data: Data_buffer;
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd := "1110";
address(1 downto 0) := "00";
Vec2Hex (address,str_8,Good2);
report "Reads multiple DWORDs from memory space! Address : "&str_8;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'1');
end RDML;
--------------------------------------------------------------------------
-- Procedure implements instruction WCFG --
--------------------------------------------------------------------------
-- writes configuration
procedure WCFG(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable read_data : Data_buffer;
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd :="1011";
address(1 downto 0) :="00"; -- linear incrementing
Vec2Hex (address,str_8,Good2);
report "Configuration write! Address : "&str_8;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'0');
end WCFG;
--------------------------------------------------------------------------
-- Procedure implements instruction RCFG --
--------------------------------------------------------------------------
-- reads configuration
procedure RCFG(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable read_data : Data_buffer;
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd :="1010";
address(1 downto 0) :="00";
Vec2Hex (address,str_8,Good2);
report "Configuration read ! Address : "&str_8;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'1');
end RCFG;
--------------------------------------------------------------------------
-- Procedure implements instruction WRIO --
--------------------------------------------------------------------------
-- writes data to IO port
procedure WRIO(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable read_data : Data_buffer;
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd := "0011";
address(1 downto 0) := "00";
Vec2Hex (address,str_8,Good2);
report "Write DWORD to I/O space! Address : "&str_8;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'0');
end WRIO;
--------------------------------------------------------------------------
-- Procedure implements instruction RDIO --
--------------------------------------------------------------------------
-- reads data from IO port
procedure RDIO(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable read_data : Data_buffer;
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
begin
bus_cmd :="0010";
address(1 downto 0) :="00";
Vec2Hex (address,str_8,Good2);
report "Read DWORD from memory space! Address : "&str_8;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'1');
end RDIO;
--------------------------------------------------------------------------
-- Procedure implements instruction WAIT --
--------------------------------------------------------------------------
-- waits
procedure CWAT(
data : in Data_buffer;
address : inout STD_LOGIC_VECTOR(31 downto 0);
data_number : in Integer;
bus_sel : in Data_Enable) is
variable bus_cmd : STD_LOGIC_VECTOR(3 downto 0);
variable str8,str_8 : string(1 to 8);
variable Good2 : Boolean;
variable byte7_6,byte5,byte4,byte3_2,byte1,byte0 : Integer;
variable Char7_6,Char5,Char4,Char3_2,Char1,Char0 : Std_Logic_Vector(7 downto 0);
begin
Char7_6 := data(1)(31 downto 24);
irdy_loop := Byte2Int(Char7_6) ;
Char5 := "0000" & data(1)(23 downto 20);
irdy_nr := Byte2Int(Char5) + 1;
Char4 := "0000" & data(1)(19 downto 16);
irdy_start := Byte2Int(Char4);
bus_cmd := "0001";
if irdy_loop = 0 or irdy_nr = 0 then
irdy_insert := false;
else
irdy_insert := true;
end if;
READ_WRITE(address,data,data_number,bus_cmd,bus_sel,'0');
end CWAT;
--------------------------------------------------------------------------
-- Procedure implements instruction EXIT --
--------------------------------------------------------------------------
-- ends the Master's activity by placing in HighZ all the lines
procedure ABRT is
begin
wait until FALLING_EDGE(CLK); -- synchro cycle
Init;
wait;
end ABRT;
--------------------------------------------------------------------------
-- Procedure implements the commands file parser and sequencer --
--------------------------------------------------------------------------
procedure Main_case is
variable Commands : CommandArray(1 to 100);
variable NumCommands : Natural;
variable Good : Boolean;
constant HeaderMsg : String := "Main process:";
constant MsgSeverity : Severity_Level := Failure;
variable ErrFlag : Boolean;
variable PC : Integer;
begin
-- Read/Parse the commands file
FileParser (cmd_file,Commands,NumCommands,ErrFlag);
data_last_read := FALSE;
if ErrFlag then
report HeaderMsg&"Errors found in COMMAND file. Execute halts!!!"
severity Warning;
else
PC := 0;
wait until RST_N = '1';
while PC < NumCommands Loop
if RESET = 1 then
RESET := 0;
PC := 0;
end if;
while RST_N = '0' loop -- RESET signal is active
PC := 0; -- if RST_N ='0' restart simulation
REQ_N <= 'H'; -- request is tri-stated
wait until Rising_Edge(CLK); -- synchro wait
end loop;
if STOP_N = '0' then
report HeaderMsg&"Wait until signal STOP_N ='0' !";
wait until STOP_N = '1';
end if;
REQ_N <= '0';
PC := PC + 1;
case Commands(pc).command is
when "WRSW" =>
WRSW(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "RDSW" =>
RDSW(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "WRMW" =>
WRMW(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "RDMW" =>
RDMW(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "RDML" =>
RDML(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "WCFG" =>
WCFG(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "RCFG" =>
RCFG(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "WRIO" =>
WRIO(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "RDIO" =>
RDIO(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "CWAT" =>
CWAT(Commands(pc).data,Commands(PC).addr,Commands(pc).data_nr,Commands(pc).Enable);
when "ABRT" => ABRT;
when others => null;
end case;
end loop;
end if;
end Main_Case;
---------------------------------------------------------------------
-- MS32PCI_MAIN : process begins
---------------------------------------------------------------------
begin
Init;
Main_case;
end process;
end Behavior; --================= End of architecture ===============--
-----------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas June 09, 2000 New model
-----------------------------------------------------------------------
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