xulieji.map.rpt

在FPGA上实现序列机 用的是Altera公司的DE1板子

; top.bdf                          ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf     ;
; hex.v                            ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/Administrator/桌面/xulieji/hex.v       ;
; ../seqdet.v                      ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/Administrator/桌面/xulieji/seqdet.v    ;
; xulieji.v                        ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/Administrator/桌面/xulieji/xulieji.v   ;
; clkA_to_B.v                      ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v ;
; decode4_7.v                      ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/Administrator/桌面/xulieji/decode4_7.v ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
;                                             ;       ;
; Total combinational functions               ; 0     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- <=2 input functions                  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 0     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
;     -- Dedicated logic registers            ; 0     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 17    ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |top                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 17   ; 0            ; |top                ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------+
; State Machine - |top|xulieji:inst7|seqdet:seqdet0|state                                       ;
+------------+---------+---------+---------+---------+---------+---------+---------+------------+
; Name       ; state.D ; state.E ; state.A ; state.B ; state.C ; state.F ; state.G ; state.IDLE ;
+------------+---------+---------+---------+---------+---------+---------+---------+------------+
; state.IDLE ; 0       ; 0       ; 0       ; 0       ; 0       ; 0       ; 0       ; 0          ;
; state.G    ; 0       ; 0       ; 0       ; 0       ; 0       ; 0       ; 1       ; 1          ;
; state.F    ; 0       ; 0       ; 0       ; 0       ; 0       ; 1       ; 0       ; 1          ;
; state.C    ; 0       ; 0       ; 0       ; 0       ; 1       ; 0       ; 0       ; 1          ;
; state.B    ; 0       ; 0       ; 0       ; 1       ; 0       ; 0       ; 0       ; 1          ;
; state.A    ; 0       ; 0       ; 1       ; 0       ; 0       ; 0       ; 0       ; 1          ;
; state.E    ; 0       ; 1       ; 0       ; 0       ; 0       ; 0       ; 0       ; 1          ;
; state.D    ; 1       ; 0       ; 0       ; 0       ; 0       ; 0       ; 0       ; 1          ;
+------------+---------+---------+---------+---------+---------+---------+---------+------------+


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; inst7/hex01/ledg                       ; Stuck at GND due to stuck port data_in ;
; inst7/hex01/h0[2]                      ; Merged with inst7/hex01/h0[3]          ;
; inst7/hex01/h1[0,3]                    ; Merged with inst7/hex01/h0[3]          ;
; inst7/hex01/h0[0]                      ; Merged with inst7/hex01/h0[3]          ;
; inst7/hex01/h1[2]                      ; Merged with inst7/hex01/h0[3]          ;
; inst7/hex01/h0[1]                      ; Merged with inst7/hex01/h0[3]          ;
; inst7/hex01/h1[1]                      ; Merged with inst7/hex01/h0[3]          ;
; inst7/hex01/h0[3]                      ; Stuck at GND due to stuck port data_in ;
; inst7/seqdet0/state~17                 ; Lost fanout                            ;
; inst7/seqdet0/state~18                 ; Lost fanout                            ;
; inst7/seqdet0/state~19                 ; Lost fanout                            ;
; inst7/clkA_B/clkB                      ; Lost fanout                            ;
; inst7/clkA_B/Q[0..23]                  ; Lost fanout                            ;
; inst7/seqdet0/state.IDLE               ; Lost fanout                            ;
; inst7/seqdet0/state.G                  ; Lost fanout                            ;
; inst7/seqdet0/state.F                  ; Lost fanout                            ;
; inst7/seqdet0/state.C                  ; Lost fanout                            ;
; inst7/seqdet0/state.B                  ; Lost fanout                            ;
; inst7/seqdet0/state.A                  ; Lost fanout                            ;
; inst7/seqdet0/state.E                  ; Lost fanout                            ;
; inst7/seqdet0/state.D                  ; Lost fanout                            ;
; Total Number of Removed Registers = 45 ;                                        ;
+----------------------------------------+----------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                      ;
+--------------------+---------------------------+---------------------------------------------------------------------------------+
; Register name      ; Reason for Removal        ; Registers Removed due to This Register                                          ;
+--------------------+---------------------------+---------------------------------------------------------------------------------+
; inst7/clkA_B/Q[23] ; Lost Fanouts              ; inst7/clkA_B/Q[22], inst7/clkA_B/Q[21], inst7/clkA_B/Q[20], inst7/clkA_B/Q[19], ;
;                    ;                           ; inst7/clkA_B/Q[18], inst7/clkA_B/Q[17], inst7/clkA_B/Q[16], inst7/clkA_B/Q[15], ;
;                    ;                           ; inst7/clkA_B/Q[14], inst7/clkA_B/Q[13], inst7/clkA_B/Q[12]                      ;
; inst7/hex01/ledg   ; Stuck at GND              ; inst7/clkA_B/clkB                                                               ;
;                    ; due to stuck port data_in ;                                                                                 ;
+--------------------+---------------------------+---------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: xulieji:inst7|seqdet:seqdet0 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; IDLE           ; 000   ; Unsigned Binary                                  ;
; A              ; 001   ; Unsigned Binary                                  ;
; B              ; 010   ; Unsigned Binary                                  ;
; C              ; 011   ; Unsigned Binary                                  ;
; D              ; 100   ; Unsigned Binary                                  ;
; E              ; 101   ; Unsigned Binary                                  ;
; F              ; 110   ; Unsigned Binary                                  ;