xulieji.hier_info

在FPGA上实现序列机 用的是Altera公司的DE1板子

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LEDG <= xulieji:inst7.z_led
clkA => xulieji:inst7.clk
rst => xulieji:inst7.rst
hex0[0] <= xulieji:inst7.hex0[0]
hex0[1] <= xulieji:inst7.hex0[1]
hex0[2] <= xulieji:inst7.hex0[2]
hex0[3] <= xulieji:inst7.hex0[3]
hex0[4] <= xulieji:inst7.hex0[4]
hex0[5] <= xulieji:inst7.hex0[5]
hex0[6] <= xulieji:inst7.hex0[6]
hex1[0] <= xulieji:inst7.hex1[0]
hex1[1] <= xulieji:inst7.hex1[1]
hex1[2] <= xulieji:inst7.hex1[2]
hex1[3] <= xulieji:inst7.hex1[3]
hex1[4] <= xulieji:inst7.hex1[4]
hex1[5] <= xulieji:inst7.hex1[5]
hex1[6] <= xulieji:inst7.hex1[6]


|top|xulieji:inst7
clk => clk~0.IN1
rst => rst~0.IN3
z_led <= hex:hex01.port5
hex0[0] <= hex:hex01.port3
hex0[1] <= hex:hex01.port3
hex0[2] <= hex:hex01.port3
hex0[3] <= hex:hex01.port3
hex0[4] <= hex:hex01.port3
hex0[5] <= hex:hex01.port3
hex0[6] <= hex:hex01.port3
hex1[0] <= hex:hex01.port4
hex1[1] <= hex:hex01.port4
hex1[2] <= hex:hex01.port4
hex1[3] <= hex:hex01.port4
hex1[4] <= hex:hex01.port4
hex1[5] <= hex:hex01.port4
hex1[6] <= hex:hex01.port4


|top|xulieji:inst7|clkA_to_B:clkA_B
clkA => Q[23].CLK
clkA => Q[22].CLK
clkA => Q[21].CLK
clkA => Q[20].CLK
clkA => Q[19].CLK
clkA => Q[18].CLK
clkA => Q[17].CLK
clkA => Q[16].CLK
clkA => Q[15].CLK
clkA => Q[14].CLK
clkA => Q[13].CLK
clkA => Q[12].CLK
clkA => Q[11].CLK
clkA => Q[10].CLK
clkA => Q[9].CLK
clkA => Q[8].CLK
clkA => Q[7].CLK
clkA => Q[6].CLK
clkA => Q[5].CLK
clkA => Q[4].CLK
clkA => Q[3].CLK
clkA => Q[2].CLK
clkA => Q[1].CLK
clkA => Q[0].CLK
clkA => clkB~reg0.CLK
rst => Q[23].ACLR
rst => Q[22].ACLR
rst => Q[21].ACLR
rst => Q[20].ACLR
rst => Q[19].ACLR
rst => Q[18].ACLR
rst => Q[17].ACLR
rst => Q[16].ACLR
rst => Q[15].ACLR
rst => Q[14].ACLR
rst => Q[13].ACLR
rst => Q[12].ACLR
rst => Q[11].ACLR
rst => Q[10].ACLR
rst => Q[9].ACLR
rst => Q[8].ACLR
rst => Q[7].ACLR
rst => Q[6].ACLR
rst => Q[5].ACLR
rst => Q[4].ACLR
rst => Q[3].ACLR
rst => Q[2].ACLR
rst => Q[1].ACLR
rst => Q[0].ACLR
rst => clkB~reg0.ENA
clkB <= clkB~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top|xulieji:inst7|seqdet:seqdet0
x => Selector0.IN0
x => Selector3.IN0
x => Selector2.IN0
x => state~0.DATAB
x => state~1.DATAB
x => z~0.IN1
x => Selector4.IN0
x => Selector1.IN0
x => state~2.DATAB
z <= z~0.DB_MAX_OUTPUT_PORT_TYPE
clk => state~3.IN1
rst => state~4.IN1


|top|xulieji:inst7|hex:hex01
clk => h0[3].CLK
clk => h0[2].CLK
clk => h0[1].CLK
clk => h0[0].CLK
clk => h1[3].CLK
clk => h1[2].CLK
clk => h1[1].CLK
clk => h1[0].CLK
clk => ledg~reg0.CLK
rst => h0[3].ACLR
rst => h0[2].ACLR
rst => h0[1].ACLR
rst => h0[0].ACLR
rst => h1[3].ACLR
rst => h1[2].ACLR
rst => h1[1].ACLR
rst => h1[0].ACLR
rst => ledg~reg0.ACLR
Y_or_NO => ledg~reg0.DATAIN
Y_or_NO => h1~15.OUTPUTSELECT
Y_or_NO => h1~14.OUTPUTSELECT
Y_or_NO => h1~13.OUTPUTSELECT
Y_or_NO => h1~12.OUTPUTSELECT
Y_or_NO => h0~11.OUTPUTSELECT
Y_or_NO => h0~10.OUTPUTSELECT
Y_or_NO => h0~9.OUTPUTSELECT
Y_or_NO => h0~8.OUTPUTSELECT
hex0[0] <= decode4_7:decode0.port0
hex0[1] <= decode4_7:decode0.port0
hex0[2] <= decode4_7:decode0.port0
hex0[3] <= decode4_7:decode0.port0
hex0[4] <= decode4_7:decode0.port0
hex0[5] <= decode4_7:decode0.port0
hex0[6] <= decode4_7:decode0.port0
hex1[0] <= decode4_7:decode1.port0
hex1[1] <= decode4_7:decode1.port0
hex1[2] <= decode4_7:decode1.port0
hex1[3] <= decode4_7:decode1.port0
hex1[4] <= decode4_7:decode1.port0
hex1[5] <= decode4_7:decode1.port0
hex1[6] <= decode4_7:decode1.port0
ledg <= ledg~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top|xulieji:inst7|hex:hex01|decode4_7:decode0
decodeout[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
decodeout[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
decodeout[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
decodeout[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
decodeout[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
decodeout[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
decodeout[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
indec[0] => Decoder0.IN3
indec[1] => Decoder0.IN2
indec[2] => Decoder0.IN1
indec[3] => Decoder0.IN0


|top|xulieji:inst7|hex:hex01|decode4_7:decode1
decodeout[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
decodeout[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
decodeout[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
decodeout[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
decodeout[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
decodeout[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
decodeout[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
indec[0] => Decoder0.IN3
indec[1] => Decoder0.IN2
indec[2] => Decoder0.IN1
indec[3] => Decoder0.IN0