prev_cmp_xulieji.tan.qmsg

在FPGA上实现序列机 用的是Altera公司的DE1板子

{ "Info" "ITDB_TSU_RESULT" "xulieji:inst7\|clkA_to_B:clkA_B\|clkB rst clk 5.984 ns register " "Info: tsu for register \"xulieji:inst7\|clkA_to_B:clkA_B\|clkB\" (data pin = \"rst\", clock pin = \"clk\") is 5.984 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.722 ns + Longest pin register " "Info: + Longest pin to register delay is 8.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns rst 1 PIN PIN_R22 41 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 41; PIN Node = 'rst'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 488 -296 -128 504 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.217 ns) + CELL(0.545 ns) 8.626 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB~16 2 COMB LCCOMB_X1_Y20_N24 1 " "Info: 2: + IC(7.217 ns) + CELL(0.545 ns) = 8.626 ns; Loc. = LCCOMB_X1_Y20_N24; Fanout = 1; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB~16'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.762 ns" { rst xulieji:inst7|clkA_to_B:clkA_B|clkB~16 } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 8.722 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB 3 REG LCFF_X1_Y20_N25 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 8.722 ns; Loc. = LCFF_X1_Y20_N25; Fanout = 2; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.505 ns ( 17.26 % ) " "Info: Total cell delay = 1.505 ns ( 17.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.217 ns ( 82.74 % ) " "Info: Total interconnect delay = 7.217 ns ( 82.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.722 ns" { rst xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.722 ns" { rst rst~combout xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 0.000ns 7.217ns 0.000ns } { 0.000ns 0.864ns 0.545ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.700 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.602 ns) 2.700 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB 2 REG LCFF_X1_Y20_N25 2 " "Info: 2: + IC(1.072 ns) + CELL(0.602 ns) = 2.700 ns; Loc. = LCFF_X1_Y20_N25; Fanout = 2; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.674 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 60.30 % ) " "Info: Total cell delay = 1.628 ns ( 60.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.072 ns ( 39.70 % ) " "Info: Total interconnect delay = 1.072 ns ( 39.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 0.000ns 1.072ns } { 0.000ns 1.026ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.722 ns" { rst xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.722 ns" { rst rst~combout xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 0.000ns 7.217ns 0.000ns } { 0.000ns 0.864ns 0.545ns 0.096ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 0.000ns 1.072ns } { 0.000ns 1.026ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk LEDG xulieji:inst7\|hex:hex01\|ledg 14.715 ns register " "Info: tco from clock \"clk\" to destination pin \"LEDG\" through register \"xulieji:inst7\|hex:hex01\|ledg\" is 14.715 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.874 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.879 ns) 2.977 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB 2 REG LCFF_X1_Y20_N25 2 " "Info: 2: + IC(1.072 ns) + CELL(0.879 ns) = 2.977 ns; Loc. = LCFF_X1_Y20_N25; Fanout = 2; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.951 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.325 ns) + CELL(0.000 ns) 4.302 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB~clkctrl 3 COMB CLKCTRL_G1 16 " "Info: 3: + IC(1.325 ns) + CELL(0.000 ns) = 4.302 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.602 ns) 5.874 ns xulieji:inst7\|hex:hex01\|ledg 4 REG LCFF_X1_Y20_N29 1 " "Info: 4: + IC(0.970 ns) + CELL(0.602 ns) = 5.874 ns; Loc. = LCFF_X1_Y20_N29; Fanout = 1; REG Node = 'xulieji:inst7\|hex:hex01\|ledg'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "hex.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/hex.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 42.68 % ) " "Info: Total cell delay = 2.507 ns ( 42.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.367 ns ( 57.32 % ) " "Info: Total interconnect delay = 3.367 ns ( 57.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.874 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } { 0.000ns 0.000ns 1.072ns 1.325ns 0.970ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "hex.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/hex.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.564 ns + Longest register pin " "Info: + Longest register to pin delay is 8.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xulieji:inst7\|hex:hex01\|ledg 1 REG LCFF_X1_Y20_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y20_N29; Fanout = 1; REG Node = 'xulieji:inst7\|hex:hex01\|ledg'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "hex.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/hex.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.714 ns) + CELL(2.850 ns) 8.564 ns LEDG 2 PIN PIN_U22 0 " "Info: 2: + IC(5.714 ns) + CELL(2.850 ns) = 8.564 ns; Loc. = PIN_U22; Fanout = 0; PIN Node = 'LEDG'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.564 ns" { xulieji:inst7|hex:hex01|ledg LEDG } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 128 304 488 "LEDG" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.850 ns ( 33.28 % ) " "Info: Total cell delay = 2.850 ns ( 33.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.714 ns ( 66.72 % ) " "Info: Total interconnect delay = 5.714 ns ( 66.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.564 ns" { xulieji:inst7|hex:hex01|ledg LEDG } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.564 ns" { xulieji:inst7|hex:hex01|ledg LEDG } { 0.000ns 5.714ns } { 0.000ns 2.850ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.874 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } { 0.000ns 0.000ns 1.072ns 1.325ns 0.970ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.564 ns" { xulieji:inst7|hex:hex01|ledg LEDG } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.564 ns" { xulieji:inst7|hex:hex01|ledg LEDG } { 0.000ns 5.714ns } { 0.000ns 2.850ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "xulieji:inst7\|hex:hex01\|ledg rst clk -2.172 ns register " "Info: th for register \"xulieji:inst7\|hex:hex01\|ledg\" (data pin = \"rst\", clock pin = \"clk\") is -2.172 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.874 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.879 ns) 2.977 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB 2 REG LCFF_X1_Y20_N25 2 " "Info: 2: + IC(1.072 ns) + CELL(0.879 ns) = 2.977 ns; Loc. = LCFF_X1_Y20_N25; Fanout = 2; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.951 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.325 ns) + CELL(0.000 ns) 4.302 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB~clkctrl 3 COMB CLKCTRL_G1 16 " "Info: 3: + IC(1.325 ns) + CELL(0.000 ns) = 4.302 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.602 ns) 5.874 ns xulieji:inst7\|hex:hex01\|ledg 4 REG LCFF_X1_Y20_N29 1 " "Info: 4: + IC(0.970 ns) + CELL(0.602 ns) = 5.874 ns; Loc. = LCFF_X1_Y20_N29; Fanout = 1; REG Node = 'xulieji:inst7\|hex:hex01\|ledg'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "hex.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/hex.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 42.68 % ) " "Info: Total cell delay = 2.507 ns ( 42.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.367 ns ( 57.32 % ) " "Info: Total interconnect delay = 3.367 ns ( 57.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.874 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } { 0.000ns 0.000ns 1.072ns 1.325ns 0.970ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "hex.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/hex.v" 7 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.332 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns rst 1 PIN PIN_R22 41 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 41; PIN Node = 'rst'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 488 -296 -128 504 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.194 ns) + CELL(0.178 ns) 8.236 ns xulieji:inst7\|hex:hex01\|ledg~8 2 COMB LCCOMB_X1_Y20_N28 1 " "Info: 2: + IC(7.194 ns) + CELL(0.178 ns) = 8.236 ns; Loc. = LCCOMB_X1_Y20_N28; Fanout = 1; COMB Node = 'xulieji:inst7\|hex:hex01\|ledg~8'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.372 ns" { rst xulieji:inst7|hex:hex01|ledg~8 } "NODE_NAME" } } { "hex.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/hex.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 8.332 ns xulieji:inst7\|hex:hex01\|ledg 3 REG LCFF_X1_Y20_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 8.332 ns; Loc. = LCFF_X1_Y20_N29; Fanout = 1; REG Node = 'xulieji:inst7\|hex:hex01\|ledg'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { xulieji:inst7|hex:hex01|ledg~8 xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "hex.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/hex.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.138 ns ( 13.66 % ) " "Info: Total cell delay = 1.138 ns ( 13.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.194 ns ( 86.34 % ) " "Info: Total interconnect delay = 7.194 ns ( 86.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.332 ns" { rst xulieji:inst7|hex:hex01|ledg~8 xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.332 ns" { rst rst~combout xulieji:inst7|hex:hex01|ledg~8 xulieji:inst7|hex:hex01|ledg } { 0.000ns 0.000ns 7.194ns 0.000ns } { 0.000ns 0.864ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.874 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|hex:hex01|ledg } { 0.000ns 0.000ns 1.072ns 1.325ns 0.970ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.332 ns" { rst xulieji:inst7|hex:hex01|ledg~8 xulieji:inst7|hex:hex01|ledg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.332 ns" { rst rst~combout xulieji:inst7|hex:hex01|ledg~8 xulieji:inst7|hex:hex01|ledg } { 0.000ns 0.000ns 7.194ns 0.000ns } { 0.000ns 0.864ns 0.178ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 30 16:23:39 2008 " "Info: Processing ended: Sun Mar 30 16:23:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}