📄 prev_cmp_xulieji.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "xulieji:inst7\|clkA_to_B:clkA_B\|clkB " "Info: Detected ripple clock \"xulieji:inst7\|clkA_to_B:clkA_B\|clkB\" as buffer" { } { { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "xulieji:inst7\|clkA_to_B:clkA_B\|clkB" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register xulieji:inst7\|clkA_to_B:clkA_B\|Q\[19\] register xulieji:inst7\|clkA_to_B:clkA_B\|clkB 213.68 MHz 4.68 ns Internal " "Info: Clock \"clk\" has Internal fmax of 213.68 MHz between source register \"xulieji:inst7\|clkA_to_B:clkA_B\|Q\[19\]\" and destination register \"xulieji:inst7\|clkA_to_B:clkA_B\|clkB\" (period= 4.68 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.298 ns + Longest register register " "Info: + Longest register to register delay is 4.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xulieji:inst7\|clkA_to_B:clkA_B\|Q\[19\] 1 REG LCFF_X9_Y20_N27 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y20_N27; Fanout = 3; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|Q\[19\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { xulieji:inst7|clkA_to_B:clkA_B|Q[19] } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.210 ns) + CELL(0.542 ns) 1.752 ns xulieji:inst7\|clkA_to_B:clkA_B\|Equal0~241 2 COMB LCCOMB_X9_Y19_N0 1 " "Info: 2: + IC(1.210 ns) + CELL(0.542 ns) = 1.752 ns; Loc. = LCCOMB_X9_Y19_N0; Fanout = 1; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|Equal0~241'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.752 ns" { xulieji:inst7|clkA_to_B:clkA_B|Q[19] xulieji:inst7|clkA_to_B:clkA_B|Equal0~241 } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.178 ns) 2.446 ns xulieji:inst7\|clkA_to_B:clkA_B\|Equal0~244 3 COMB LCCOMB_X9_Y20_N28 5 " "Info: 3: + IC(0.516 ns) + CELL(0.178 ns) = 2.446 ns; Loc. = LCCOMB_X9_Y20_N28; Fanout = 5; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|Equal0~244'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.694 ns" { xulieji:inst7|clkA_to_B:clkA_B|Equal0~241 xulieji:inst7|clkA_to_B:clkA_B|Equal0~244 } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.178 ns) 3.722 ns xulieji:inst7\|clkA_to_B:clkA_B\|Equal0~247 4 COMB LCCOMB_X1_Y20_N18 1 " "Info: 4: + IC(1.098 ns) + CELL(0.178 ns) = 3.722 ns; Loc. = LCCOMB_X1_Y20_N18; Fanout = 1; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|Equal0~247'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.276 ns" { xulieji:inst7|clkA_to_B:clkA_B|Equal0~244 xulieji:inst7|clkA_to_B:clkA_B|Equal0~247 } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.178 ns) 4.202 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB~16 5 COMB LCCOMB_X1_Y20_N24 1 " "Info: 5: + IC(0.302 ns) + CELL(0.178 ns) = 4.202 ns; Loc. = LCCOMB_X1_Y20_N24; Fanout = 1; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB~16'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.480 ns" { xulieji:inst7|clkA_to_B:clkA_B|Equal0~247 xulieji:inst7|clkA_to_B:clkA_B|clkB~16 } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 4.298 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB 6 REG LCFF_X1_Y20_N25 2 " "Info: 6: + IC(0.000 ns) + CELL(0.096 ns) = 4.298 ns; Loc. = LCFF_X1_Y20_N25; Fanout = 2; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.172 ns ( 27.27 % ) " "Info: Total cell delay = 1.172 ns ( 27.27 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.126 ns ( 72.73 % ) " "Info: Total interconnect delay = 3.126 ns ( 72.73 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.298 ns" { xulieji:inst7|clkA_to_B:clkA_B|Q[19] xulieji:inst7|clkA_to_B:clkA_B|Equal0~241 xulieji:inst7|clkA_to_B:clkA_B|Equal0~244 xulieji:inst7|clkA_to_B:clkA_B|Equal0~247 xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.298 ns" { xulieji:inst7|clkA_to_B:clkA_B|Q[19] xulieji:inst7|clkA_to_B:clkA_B|Equal0~241 xulieji:inst7|clkA_to_B:clkA_B|Equal0~244 xulieji:inst7|clkA_to_B:clkA_B|Equal0~247 xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 1.210ns 0.516ns 1.098ns 0.302ns 0.000ns } { 0.000ns 0.542ns 0.178ns 0.178ns 0.178ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.143 ns - Smallest " "Info: - Smallest clock skew is -0.143 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.700 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.602 ns) 2.700 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB 2 REG LCFF_X1_Y20_N25 2 " "Info: 2: + IC(1.072 ns) + CELL(0.602 ns) = 2.700 ns; Loc. = LCFF_X1_Y20_N25; Fanout = 2; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.674 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 60.30 % ) " "Info: Total cell delay = 1.628 ns ( 60.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.072 ns ( 39.70 % ) " "Info: Total interconnect delay = 1.072 ns ( 39.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 0.000ns 1.072ns } { 0.000ns 1.026ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.843 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 49 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 49; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.977 ns) + CELL(0.602 ns) 2.843 ns xulieji:inst7\|clkA_to_B:clkA_B\|Q\[19\] 3 REG LCFF_X9_Y20_N27 3 " "Info: 3: + IC(0.977 ns) + CELL(0.602 ns) = 2.843 ns; Loc. = LCFF_X9_Y20_N27; Fanout = 3; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|Q\[19\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.579 ns" { clk~clkctrl xulieji:inst7|clkA_to_B:clkA_B|Q[19] } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.26 % ) " "Info: Total cell delay = 1.628 ns ( 57.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.215 ns ( 42.74 % ) " "Info: Total interconnect delay = 1.215 ns ( 42.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl xulieji:inst7|clkA_to_B:clkA_B|Q[19] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl xulieji:inst7|clkA_to_B:clkA_B|Q[19] } { 0.000ns 0.000ns 0.238ns 0.977ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 0.000ns 1.072ns } { 0.000ns 1.026ns 0.602ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl xulieji:inst7|clkA_to_B:clkA_B|Q[19] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl xulieji:inst7|clkA_to_B:clkA_B|Q[19] } { 0.000ns 0.000ns 0.238ns 0.977ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 14 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.298 ns" { xulieji:inst7|clkA_to_B:clkA_B|Q[19] xulieji:inst7|clkA_to_B:clkA_B|Equal0~241 xulieji:inst7|clkA_to_B:clkA_B|Equal0~244 xulieji:inst7|clkA_to_B:clkA_B|Equal0~247 xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.298 ns" { xulieji:inst7|clkA_to_B:clkA_B|Q[19] xulieji:inst7|clkA_to_B:clkA_B|Equal0~241 xulieji:inst7|clkA_to_B:clkA_B|Equal0~244 xulieji:inst7|clkA_to_B:clkA_B|Equal0~247 xulieji:inst7|clkA_to_B:clkA_B|clkB~16 xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 1.210ns 0.516ns 1.098ns 0.302ns 0.000ns } { 0.000ns 0.542ns 0.178ns 0.178ns 0.178ns 0.096ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.700 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB } { 0.000ns 0.000ns 1.072ns } { 0.000ns 1.026ns 0.602ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl xulieji:inst7|clkA_to_B:clkA_B|Q[19] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk clk~combout clk~clkctrl xulieji:inst7|clkA_to_B:clkA_B|Q[19] } { 0.000ns 0.000ns 0.238ns 0.977ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 16 " "Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "xulieji:inst7\|data\[0\] xulieji:inst7\|seqdet:seqdet0\|state.E clk 1.825 ns " "Info: Found hold time violation between source pin or register \"xulieji:inst7\|data\[0\]\" and destination pin or register \"xulieji:inst7\|seqdet:seqdet0\|state.E\" for clock \"clk\" (Hold time is 1.825 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.035 ns + Largest " "Info: + Largest clock skew is 3.035 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.874 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.072 ns) + CELL(0.879 ns) 2.977 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB 2 REG LCFF_X1_Y20_N25 2 " "Info: 2: + IC(1.072 ns) + CELL(0.879 ns) = 2.977 ns; Loc. = LCFF_X1_Y20_N25; Fanout = 2; REG Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.951 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.325 ns) + CELL(0.000 ns) 4.302 ns xulieji:inst7\|clkA_to_B:clkA_B\|clkB~clkctrl 3 COMB CLKCTRL_G1 16 " "Info: 3: + IC(1.325 ns) + CELL(0.000 ns) = 4.302 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'xulieji:inst7\|clkA_to_B:clkA_B\|clkB~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl } "NODE_NAME" } } { "clkA_to_B.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/clkA_to_B.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.602 ns) 5.874 ns xulieji:inst7\|seqdet:seqdet0\|state.E 4 REG LCFF_X1_Y20_N31 1 " "Info: 4: + IC(0.970 ns) + CELL(0.602 ns) = 5.874 ns; Loc. = LCFF_X1_Y20_N31; Fanout = 1; REG Node = 'xulieji:inst7\|seqdet:seqdet0\|state.E'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|seqdet:seqdet0|state.E } "NODE_NAME" } } { "seqdet.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/seqdet.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 42.68 % ) " "Info: Total cell delay = 2.507 ns ( 42.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.367 ns ( 57.32 % ) " "Info: Total interconnect delay = 3.367 ns ( 57.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|seqdet:seqdet0|state.E } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.874 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|seqdet:seqdet0|state.E } { 0.000ns 0.000ns 1.072ns 1.325ns 0.970ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.839 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.839 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 49 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 49; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "top.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/xulieji/top.bdf" { { 472 -296 -128 488 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.973 ns) + CELL(0.602 ns) 2.839 ns xulieji:inst7\|data\[0\] 3 REG LCFF_X5_Y20_N21 11 " "Info: 3: + IC(0.973 ns) + CELL(0.602 ns) = 2.839 ns; Loc. = LCFF_X5_Y20_N21; Fanout = 11; REG Node = 'xulieji:inst7\|data\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { clk~clkctrl xulieji:inst7|data[0] } "NODE_NAME" } } { "xulieji.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/xulieji.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.34 % ) " "Info: Total cell delay = 1.628 ns ( 57.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.211 ns ( 42.66 % ) " "Info: Total interconnect delay = 1.211 ns ( 42.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.839 ns" { clk clk~clkctrl xulieji:inst7|data[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.839 ns" { clk clk~combout clk~clkctrl xulieji:inst7|data[0] } { 0.000ns 0.000ns 0.238ns 0.973ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|seqdet:seqdet0|state.E } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.874 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|seqdet:seqdet0|state.E } { 0.000ns 0.000ns 1.072ns 1.325ns 0.970ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.839 ns" { clk clk~clkctrl xulieji:inst7|data[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.839 ns" { clk clk~combout clk~clkctrl xulieji:inst7|data[0] } { 0.000ns 0.000ns 0.238ns 0.973ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" { } { { "xulieji.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/xulieji.v" 9 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.219 ns - Shortest register register " "Info: - Shortest register to register delay is 1.219 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xulieji:inst7\|data\[0\] 1 REG LCFF_X5_Y20_N21 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y20_N21; Fanout = 11; REG Node = 'xulieji:inst7\|data\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { xulieji:inst7|data[0] } "NODE_NAME" } } { "xulieji.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/xulieji.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.177 ns) 1.123 ns xulieji:inst7\|seqdet:seqdet0\|z 2 COMB LCCOMB_X1_Y20_N30 1 " "Info: 2: + IC(0.946 ns) + CELL(0.177 ns) = 1.123 ns; Loc. = LCCOMB_X1_Y20_N30; Fanout = 1; COMB Node = 'xulieji:inst7\|seqdet:seqdet0\|z'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { xulieji:inst7|data[0] xulieji:inst7|seqdet:seqdet0|z } "NODE_NAME" } } { "seqdet.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/seqdet.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.219 ns xulieji:inst7\|seqdet:seqdet0\|state.E 3 REG LCFF_X1_Y20_N31 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 1.219 ns; Loc. = LCFF_X1_Y20_N31; Fanout = 1; REG Node = 'xulieji:inst7\|seqdet:seqdet0\|state.E'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { xulieji:inst7|seqdet:seqdet0|z xulieji:inst7|seqdet:seqdet0|state.E } "NODE_NAME" } } { "seqdet.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/seqdet.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.273 ns ( 22.40 % ) " "Info: Total cell delay = 0.273 ns ( 22.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.946 ns ( 77.60 % ) " "Info: Total interconnect delay = 0.946 ns ( 77.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.219 ns" { xulieji:inst7|data[0] xulieji:inst7|seqdet:seqdet0|z xulieji:inst7|seqdet:seqdet0|state.E } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.219 ns" { xulieji:inst7|data[0] xulieji:inst7|seqdet:seqdet0|z xulieji:inst7|seqdet:seqdet0|state.E } { 0.000ns 0.946ns 0.000ns } { 0.000ns 0.177ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" { } { { "seqdet.v" "" { Text "C:/Documents and Settings/Administrator/桌面/xulieji/seqdet.v" 4 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { clk xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|seqdet:seqdet0|state.E } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.874 ns" { clk clk~combout xulieji:inst7|clkA_to_B:clkA_B|clkB xulieji:inst7|clkA_to_B:clkA_B|clkB~clkctrl xulieji:inst7|seqdet:seqdet0|state.E } { 0.000ns 0.000ns 1.072ns 1.325ns 0.970ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.839 ns" { clk clk~clkctrl xulieji:inst7|data[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.839 ns" { clk clk~combout clk~clkctrl xulieji:inst7|data[0] } { 0.000ns 0.000ns 0.238ns 0.973ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.219 ns" { xulieji:inst7|data[0] xulieji:inst7|seqdet:seqdet0|z xulieji:inst7|seqdet:seqdet0|state.E } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.219 ns" { xulieji:inst7|data[0] xulieji:inst7|seqdet:seqdet0|z xulieji:inst7|seqdet:seqdet0|state.E } { 0.000ns 0.946ns 0.000ns } { 0.000ns 0.177ns 0.096ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
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