seqdet.v.bak

在FPGA上实现序列机 用的是Altera公司的DE1板子

module seqdet(x,z,clk,rst); 
input x,clk,rst; 
output z; 
reg[2:0] state; 
wire z; 
parameter IDLE=3'd0, 
		  A=3'd1, 
		  B=3'd2, 
		  C=3'd3, 
		  D=3'd4, 
		  E=3'd5, 
		  F=3'd6, 
		  G=3'd7; 
assign z=(state==D && x==1)?1:0; 
always@(posedge clk or negedge rst) 
begin
	if(!rst) 
	begin 
		state<=IDLE; 
	end 
	else 
	casex(state) 
		IDLE:if(x==0)  state<=A;				 
		     else state<=IDLE; 		
		A:   if(x==1) state<=B;		 
		     else state<=A; 
		B:   if(x==1) state<=C;
		     else state<=F; 		
		C:   if(x==0) state<=D;
		     else state<=G; 		
		D:   if(x==1) state<=E; 		
		     else state<=A; 
		E:   if(x==1) state<=C;
		     else state<=A; 
		F:   if(x==0) state<=A; 
		     else state<=B; 
		G:   if(x==0) state<=F;
		     else state<=G; 
		default: state<=IDLE; 
	endcase 
end
endmodule