xulieji.tan.summary

来自「在FPGA上实现序列机 用的是Altera公司的DE1板子」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.984 ns
From           : rst
To             : xulieji:inst7|clkA_to_B:clkA_B|clkB
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.715 ns
From           : xulieji:inst7|hex:hex01|ledg
To             : LEDG
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.172 ns
From           : rst
To             : xulieji:inst7|hex:hex01|ledg
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 213.68 MHz ( period = 4.680 ns )
From           : xulieji:inst7|clkA_to_B:clkA_B|Q[19]
To             : xulieji:inst7|clkA_to_B:clkA_B|clkB
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : xulieji:inst7|data[0]
To             : xulieji:inst7|seqdet:seqdet0|state.E
From Clock     : clk
To Clock       : clk
Failed Paths   : 16

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 16

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