xulieji.qsf

在FPGA上实现序列机 用的是Altera公司的DE1板子

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		xulieji_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:49:44  MARCH 28, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name SOURCE_FILE xulieji.qsf
set_global_assignment -name BDF_FILE top.bdf
set_global_assignment -name BSF_FILE xulieji.bsf
set_global_assignment -name BSF_FILE decode4_7.bsf
set_global_assignment -name BSF_FILE hex.bsf
set_global_assignment -name VERILOG_FILE hex.v
set_global_assignment -name VERILOG_FILE ../seqdet.v
set_global_assignment -name VERILOG_FILE xulieji.v
set_global_assignment -name VERILOG_FILE clkA_to_B.v
set_location_assignment PIN_R22 -to rst
set_location_assignment PIN_J2 -to hex0[0]
set_location_assignment PIN_J1 -to hex0[1]
set_location_assignment PIN_H2 -to hex0[2]
set_location_assignment PIN_H1 -to hex0[3]
set_location_assignment PIN_F2 -to hex0[4]
set_location_assignment PIN_F1 -to hex0[5]
set_location_assignment PIN_E2 -to hex0[6]
set_location_assignment PIN_E1 -to hex1[0]
set_location_assignment PIN_H6 -to hex1[1]
set_location_assignment PIN_H5 -to hex1[2]
set_location_assignment PIN_H4 -to hex1[3]
set_location_assignment PIN_G3 -to hex1[4]
set_location_assignment PIN_D2 -to hex1[5]
set_location_assignment PIN_D1 -to hex1[6]
set_location_assignment PIN_L1 -to clk
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name VERILOG_FILE decode4_7.v
set_location_assignment PIN_U22 -to LEDG
set_location_assignment PIN_L1 -to clkA